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The transition of the transistors occurs when the error
changes its sign and exceeds 0 of a value Δ.
If output at the controller is a signal high (1), are controlled in
closing T1 and T3, and T2 and T4 in openings.
Vice versa if the signal is low (0), are controlled in closing T2
and T4, and in the opening T1 and T3.
Consider the case in which the current signal I is an ideal sinusoidal
o
and the load to be supplied both RL with a time constant very long.
Trend of the
sinusoidal current
into an RL load
Consider now the case in which you want to power the load RL with a
constant current I o Trend of the
constant current
into an RL load
CONTROL DIAGRAM – Three Phase Loads
Suppose we have a three-phase load predominantly inductive and with
the neutral connected directly to the central point of the battery
Fig.4
CONTROL DIAGRAM – Three Phase Loads
Fig.5 Representation of
bandwidth HB (i )
a
Limit of the vector Is*
Supposing to carry out the control, no longer in the reference system a,
b, c, but in the fixed system α, β, we introduce the space vector of the
current Is.
This vector also present limits of variation, which are presented in fig. 6
hexagon marked. Fig.6
Problem of this method
The control scheme in the Laplace domain is:
Block diagram of the Adjusting system with hysteresis in the d, q
δd and δq can be alone or > 0 or < 0; analysis of the sign
represents the method for choosing the voltage to be
generated.
Choice of configurations
The choice of the voltage vector to be generated is not
univocal; you choose the tension that involves the least
number of commutations.
With this type of control is never used the 'zero-configuration'
inverter.
To use it, the characteristic of the regulator hysteresis must
be:
In Field Oriented Control, the components i and i define
sd sq
the vector of the current I * that remains constant to regime,
s
in the reference d, q.
The current error ΔI is zero under ideal setting, ie when the
s
actual current vector Is equals the reference I .
sa
However, being an ideal condition is that: if we denote by
ΔI the maximum permissible error in the plan d, q, the I
s s
max
vector must move in a circle with center in I * and radius
s
equal to ΔI .
smax
Limit of I in d,q axes
s Each time that I meets the circle,
s
is changed status of the inverter in
order to generate a voltage vector
V to bring back inside the
sk
perimeter of limit.
Since more than one solution
satisfies this condition, you choose
that vector that maximizes the time
interval for which there is the
occurrence of another intersection,
in other words it tends to adopt the
solution that minimizes the
switching frequency.
Simplified circuits Fig.7
by placing