Motorola 68000 - Microprocessors User’s Manual

INTERNAL SIGNAL VALID

EXTERNAL SIGNAL SAMPLED

CLK

BR (EXTERNAL) 47

BR (iNTERNAL)

Figure 5-17. External Asynchronous Signal Synchronization

Bus arbitration control is implemented with a finite-state machine. State diagram (a) in

Figure 5-18 applies to all processors using 3-wire bus arbitration and state diagram (b)

applies to processors using 2-wire bus arbitration, in which is permanently

BGACK

negated internally or externally. The same finite-state machine is used, but it is effectively

a two-state machine because is always negated.

BGACK

In Figure 5-18, input signals R and A are the internally synchronized versions of and

BR

The output is shown as G, and the internal three-state control signal is shown

BGACK. BG

as T. If T is true, the address, data, and control buses are placed in the high-impedance

state when is negated. All signals are shown in positive logic (active high), regardless

AS

of their true active voltage level. State changes (valid outputs) occur on the next rising

edge of the clock after the internal signal is valid.

A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in

Figure 5-19. The bus arbitration timing while the bus is inactive (e.g., the processor is

performing internal operations for a multiply instruction) is shown in Figure 5-20.

When a bus request is made after the MPU has begun a bus cycle and before has

AS

been asserted (S0), the special sequence shown in Figure 5-21 applies. Instead of being

asserted on the next rising edge of clock, is delayed until the second rising edge

BG

following its internal assertion.

5-16 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

RA

1 1

GT XA

RA RA

GT RA GT

RA

RA R+A

XX RX

GT

XA RA

GT GT

RA

RA XX

RA GT RA

(a) 3-Wire Bus Arbitration

R

GT

R R

STATE 0 GT

R

GT STATE 4

STATE 1

X GT X

STATE 3

GT

STATE 2 R

(b) 2-Wire Bus Arbitration

R Notes:

1. State machine will not change if

R = Bus Request Internal the bus is S0 or S1. Refer to

A = Bus Grant Acknowledge Internal 5.2.3.

BUS ARBITRATION CONTROL.

G = Bus Grant 2. The address bus will be placed in

T = Three-state Control to Bus Control Logic the high-impedance state if T is

X = Don't Care asserted and is negated.

AS

Figure 5-18. Bus Arbitration Unit State Diagrams

Figures 5-19, 5-20, and 5-21 applies to all processors using 3-wire bus arbitration. Figures

5-22, 5-23, and 5-24 applies to all processors using 2-wire bus arbitration.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-17

BUS THREE-STATED BUS RELEASED FROM THREE STATE AND

BG ASSERTED PROCESSOR STARTS NEXT BUS CYCLE

BR VALID INTERNAL BGACK NEGATED INTERNAL

BR SAMPLED BGACK SAMPLED

BR ASSERTED BGACK NEGATED

CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1

BR

BG

BGACK

FC2–FC0

A23–A1

AS

UDS

LDS

R/W

DTACK

D15–D0 PROCESSOR ALTERNATE BUS MASTER PROCESSOR

Figure 5-19. 3-Wire Bus Arbitration Timing Diagram—Processor Active

5-18 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE

BGACK NEGATED

BG ASSERTED AND BUS THREE STATED

BR VALID INTERNAL

BR SAMPLED

BR ASSERTED

CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4

BR

BG

BGACK

FC2–FC0

A23–A1

AS

UDS

LDS

R/W

DTACK

D15–D0 BUS

PROCESSOR INACTIVE ALTERNATE BUS MASTER PROCESSOR

Figure 5-20. 3-Wire Bus Arbitration Timing Diagram—Bus Inactive

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-19

BUS THREE-STATED BUS RELEASED FROM THREE STATE AND

BG ASSERTED PROCESSOR STARTS NEXT BUS CYCLE

BR VALID INTERNAL BGACK NEGATED INTERNAL

BR SAMPLED BGACK SAMPLED

BR ASSERTED BGACK NEGATED

CLK S0 S2 S4 S6 S0 S2 S4 S6 S0

BR

BG

BGACK

FC2–FC0

A23–A1

AS

UDS

LDS

R/W

DTACK

D15–D0 PROCESSOR ALTERNATE BUS MASTER PROCESSOR

Figure 5-21. 3-Wire Bus Arbitration Timing Diagram—Special Case

5-20 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

BUS THREE-STATED BUS RELEASED FROM THREE STATE AND

BG ASSERTED PROCESSOR STARTS NEXT BUS CYCLE

BR VALID INTERNAL BR NEGATED INTERNAL

BR SAMPLED BR SAMPLED

BR ASSERTED BR NEGATED

CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1

BR

BG

BGACK

FC2–FC0

A23–A1

AS

UDS

LDS

R/W

DTACK

D15–D0 ALTERNATE BUS MASTER PROCESSOR

PROCESSOR

Figure 5-22. 2-Wire Bus Arbitration Timing Diagram—Processor Active

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-21

BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE

BR NEGATED

BG ASSERTED AND BUS THREE STATED

BR VALID INTERNAL

BR SAMPLED

BR ASSERTED

CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4

BR

BG

BGACK

FC2–FC0

A23–A1

AS

UDS

LDS

R/W

DTACK

D15–D0 BUS ALTERNATE BUS MASTER PROCESSOR

PROCESSOR INACTIVE

Figure 5-23. 2-Wire Bus Arbitration Timing Diagram—Bus Inactive

5-22 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

BUS THREE-STATED BUS RELEASED FROM THREE STATE AND

BG ASSERTED PROCESSOR STARTS NEXT BUS CYCLE

BR VALID INTERNAL BR NEGATED INTERNAL

BR SAMPLED BR SAMPLED

BR ASSERTED BR NEGATED

CLK S0 S2 S4 S6 S0 S2 S4 S6 S0

BR

BG

BGACK

FC2–FC0

A23–A1

AS

UDS

LDS

R/W

DTACK

D15–D0 ALTERNATE BUS MASTER PROCESSOR

PROCESSOR

Figure 5-24. 2-Wire Bus Arbitration Timing Diagram—Special Case

5.4. BUS ERROR AND HALT OPERATION

In a bus architecture that requires a handshake from an external device, such as the

asynchronous bus used in the M68000 Family, the handshake may not always occur. A

bus error input is provided to terminate a bus cycle in error when the expected signal is

not asserted. Different systems and different devices within the same system require

different maximum-response times. External circuitry can be provided to assert the bus

error signal after the appropriate delay following the assertion of address strobe.

In a virtual memory system, the bus error signal can be used to indicate either a page fault

or a bus timeout. An external memory management unit asserts bus error when the page

that contains the required data is not resident in memory. The processor suspends

execution of the current instruction while the page is loaded into memory. The MC68010

pushes enough information on the stack to be able to resume execution of the instruction

following return from the bus error exception handler.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-23

The MC68010 also differs from the other microprocessors described in this manual

regarding bus errors. The MC68010 can detect a late bus error signal asserted within one

clock cycle after the assertion of data transfer acknowledge. When receiving a bus error

signal, the processor can either initiate a bus error exception sequence or try running the

cycle again.

5.4.1 Bus Error Operation

In all the microprocessors described in this manual, a bus error is recognized when

and are negated and is asserted. In the MC68010, a late bus error is

DTACK HALT BERR

also recognized when is negated, and and are asserted within one

HALT DTACK BERR

clock cycle.

When the bus error condition is recognized, the current bus cycle is terminated in S9 for a

read cycle, a write cycle, or the read portion of a read-modify-write cycle. For the write

portion of a read-modify-write cycle, the current bus cycle is terminated in S21. As long as

remains asserted, the data and address buses are in the high-impedance state.

BERR

Figure 5-25 shows the timing for the normal bus error, and Figure 5-26 shows the timing

for the MC68010 late bus error.

S0 S2 S4 w w w

w S6 S8

CLK

FC2–FC0

A23–A1

AS

LDS/UDS

R/W

DTACK

D15–D0

BERR

HALT INITIATE INITIATE BUS

RESPONSE BUS ERROR

READ FAILURE DETECTION ERROR STACKING

Figure 5-25. Bus Error Timing Diagram

5-24 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

S0 S2 S4 S6

CLK

FC2–FC0

A23–A1

AS

UDS/LDS

R/W

DTACK

D15–D0

BERR

HALT BUS ERROR INITIATE BUS

READ CYCLE DETECTION ERROR STACKING

Figure 5-26. Delayed Bus Error Timing Diagram (MC68010)

After the aborted bus cycle is terminated and is negated, the processor enters

BERR

exception processing for the bus error exception. During the exception processing

sequence, the following information is placed on the supervisor stack:

1. Status register

2. Program counter (two words, which may be up to five words past the instruction

being executed)

3. Error information

The first two items are identical to the information stacked by any other exception. The

error information differs for the MC68010. The MC68000, MC68HC000, MC68HC001,

MC68EC000, and MC68008 stack bus error information to help determine and to correct

the error. The MC68010 stacks the frame format and the vector offset followed by 22

words of internal register information. The return from exception (RTE) instruction restores

the internal register information so that the MC68010 can continue execution of the

instruction after the error handler routine completes.

After the processor has placed the required information on the stack, the bus error

exception vector is read from vector table entry 2 (offset $08) and placed in the program

counter. The processor resumes execution at the address in the vector, which is the first

instruction in the bus error handler routine.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-25

NOTE

In the MC68010, if a read-modify-write operation terminates in

a bus error, the processor reruns the entire read-modify-write

operation when the RTE instruction at the end of the bus error

handler returns control to the instruction in error. The

processor reruns the entire operation whether the error

occurred during the read or write portion.

5.4.2 Retrying The Bus Cycle

The assertion of the bus error signal during a bus cycle in which is also asserted by

HALT

an external device initiates a retry operation. Figure 5-27 is a timing diagram of the retry

operation. The delayed signal in the MC68010 also initiates a retry operation when

BERR

is asserted by an external device. Figure 5-28 shows the timing of the delayed

HALT

operation. S0 S2 S4 S6 S8 S0 S2 S4 S6

CLK

FC2-FC0

A23–A1

AS

LDS/UDS

R/W

DTACK

D15–D0

BERR ≥ 1 CLOCK PERIOD

HALT READ HALT RETRY

Figure 5-27. Retry Bus Cycle Timing Diagram

5-26 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

S0 S2 S4 S6 S0 S2 S4 S6

CLK

FC2–FC0

A23–A1

AS

UDS

LDS

R/W

DTACK

D0–D15

BERR

HALT READ HALT RETRY

Figure 5-28. Delayed Retry Bus Cycle Timing Diagram

The processor terminates the bus cycle, then puts the address and data lines in the high-

impedance state. The processor remains in this state until is negated. Then the

HALT

processor retries the preceding cycle using the same function codes, address, and data

(for a write operation). should be negated at least one clock cycle before is

BERR HALT

negated. NOTE

To guarantee that the entire read-modify-write cycle runs

correctly and that the write portion of the operation is

performed without negating the address strobe, the processor

does not retry a read-modify-write cycle. When a bus error

occurs during a read-modify-write operation, a bus error

operation is performed whether or not is asserted.

HALT

HALT)

5.4.3 Halt Operation (

performs a halt/run/single-step operation similar to the halt operation of an

HALT

MC68000. When is asserted by an external device, the processor halts and remains

HALT

halted as long as the signal remains asserted, as shown in Figure 5-29.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-27

S0 S2 S4 S6 S0 S2 S4 S6

CLK

FC2–FC0

A23–A1

AS

UDS

LDS

R/W

DTACK

D0–D15

BERR

HALT RETRY

READ HALT

Figure 5-29. Halt Operation Timing Diagram

While the processor is halted, the address bus and the data bus signals are placed in the

high-impedance state. Bus arbitration is performed as usual. Should a bus error occur

while is asserted, the processor performs the retry operation previously described.

HALT

The single-step mode is derived from correctly timed transitions of is negated

HALT. HALT

to allow the processor to begin a bus cycle, then asserted to enter the halt mode when the

cycle completes. The single-step mode proceeds through a program one bus cycle at a

time for debugging purposes. The halt operation and the hardware trace capability allow

tracing of either bus cycles or instructions one at a time. These capabilities and a software

debugging package provide total debugging flexibility.

5.4.4 Double Bus Fault

When a bus error exception occurs, the processor begins exception processing by

stacking information on the supervisor stack. If another bus error occurs during exception

processing (i.e., before execution of another instruction begins) the processor halts and

asserts This is called a double bus fault. Only an external reset operation can

HALT.

restart a processor halted due to a double bus fault.

A retry operation does not initiate exception processing; a bus error during a retry

operation does not cause a double bus fault. The processor can continue to retry a bus

cycle indefinitely if external hardware requests.

5-28 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

A double bus fault occurs during a reset operation when a bus error occurs while the

processor is reading the vector table (before the first instruction is executed). The reset

operation is described in the following paragraph.

5.5 RESET OPERATION

is asserted externally for the initial processor reset. Subsequently, the signal can

RESET

be asserted either externally or internally (executing a RESET instruction). For proper

external reset operation, must also be asserted.

HALT

When and are driven by an external device, the entire system, including the

RESET HALT

processor, is reset. Resetting the processor initializes the internal state. The processor

reads the reset vector table entry (address $00000) and loads the contents into the

supervisor stack pointer (SSP). Next, the processor loads the contents of address $00004

(vector table entry 1) into the program counter. Then the processor initializes the interrupt

level in the status register to a value of seven. In the MC68010, the processor also clears

the vector base register to $00000. No other register is affected by the reset sequence.

Figure 5-30 shows the timing of the reset operation.

CLK

+ 5 VOLTS

VCC ≥

T 100 MILLISECONDS

RESET

HALT < 1

T 4 CLOCKS

BUS CYCLES 2 3 4 5 6

NOTES:

1. Internal start-up time 4. PC High read in here Bus State Unknown:

2. SSP high read in here 5. PC Low read in here

3. SSP low read in here 6. First instruction fetched here All Control Signals Inactive.

Data Bus in Read Mode:

Figure 5-30. Reset Operation Timing Diagram

The RESET instruction causes the processor to assert for 124 clock periods to

RESET

reset the external devices of the system. The internal state of the processor is not

affected. Neither the status register nor any of the internal registers is affected by an

internal reset operation. All external devices in the system should be reset at the

completion of the RESET instruction.

For the initial reset, and must be asserted for at least 100 ms. For a

RESET HALT

subsequent external reset, asserting these signals for 10 clock cycles or longer resets the

processor. However, an external reset signal that is asserted while the processor is

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-29

executing a reset instruction is ignored. Since the processor asserts the signal for

RESET

124 clock cycles during execution of a reset instruction, an external reset should assert

for at least 132 clock periods.

RESET DTACK BERR HALT

5.6 THE RELATIONSHIP OF , , AND

To properly control termination of a bus cycle for a retry or a bus error condition, DTACK,

and should be asserted and negated on the rising edge of the processor

BERR, HALT

clock. This relationship assures that when two signals are asserted simultaneously, the

required setup time (specification #47, Section 9 Electrical Characteristics) for both of

them is met during the same bus state. External circuitry should be designed to

incorporate this precaution. A related specification, #48, can be ignored when DTACK,

and are asserted and negated on the rising edge of the processor clock.

BERR, HALT

The possible bus cycle termination can be summarized as follows (case numbers refer to

Table 5-5).

Normal Termination: is asserted. and remain negated (case 1).

DTACK BERR HALT

Halt Termination: is asserted coincident with or preceding and

HALT DTACK,

remains negated (case 2).

BERR

Bus Error Termination: is asserted in lieu of, coincident with, or preceding

BERR (case 3). In the MC68010, the late bus error also,

DTACK

is asserted following (case 4). remains

BERR DTACK HALT

negated and is negated coincident with or after

BERR DTACK.

Retry Termination: and asserted in lieu of, coincident with, or before

HALT BERR

(case 5). In the MC68010, the late retry also,

DTACK BERR

and are asserted following (case 6). is

HALT DTACK BERR

negated coincident with or after must be held at

DTACK. HALT

least one cycle after BERR.

Table 5-1 shows the details of the resulting bus cycle termination in the M68000

microprocessors for various combinations of signal sequences.

5-30 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

DTACK BERR HALT

Table 5-1. , , and Assertion Results

Asserted on

Case Control Rising Edge MC68000/MC68HC000/001 MC68010 Results

No. Signal of State EC000/MC68008 Results

N N+2

1 A S Normal cycle terminate and continue. Normal cycle terminate and continue.

DTACK NA NA

BERR NA X

HALT

2 A S Normal cycle terminate and halt. Normal cycle terminate and halt.

DTACK NA NA Continue when negated. Continue when negated.

BERR HALT HALT

A/S S

HALT

3 X X Terminate and take bus error trap. Terminate and take bus error trap.

DTACK A S

BERR NA NA

HALT

4 A S Normal cycle terminate and continue. Terminate and take bus error trap.

DTACK NA A

BERR NA NA

HALT

5 X X Terminate and retry when Terminate and retry when

DTACK HALT HALT

A S removed. removed.

BERR A/S S

HALT

6 A S Normal cycle terminate and continue. Terminate and retry when

DTACK HALT

NA A removed.

BERR NA A

HALT

LEGEND:

N — The number of the current even bus state (e.g., S4, S6, etc.)

A — Signal asserted in this bus state

NA — Signal not asserted in this bus state

X — Don't care

S — Signal asserted in preceding bus state and remains asserted in this state

NOTE: All operations are subject to relevant setup and hold times.

The negation of and under several conditions is shown in Table 5-6. (DTACK

BERR HALT

is assumed to be negated normally in all cases; for reliable operation, both and

DTACK

should be negated when address strobe is negated).

BERR

EXAMPLE A:

A system uses a watchdog timer to terminate accesses to unused address space. The

timer asserts after timeout (case 3).

BERR

EXAMPLE B:

A system uses error detection on random-access memory (RAM) contents. The system

designer may:

1. Delay until the data is verified. If data is invalid, return and

DTACK BERR HALT

simultaneously to retry the error cycle (case 5).

2. Delay until the data is verified. If data is invalid, return at the same

DTACK BERR

time as (case 3).

DTACK

3. For an MC68010, return before data verification. If data is invalid, assert

DTACK

and to retry the error cycle (case 6).

BERR HALT

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-31

4. For an MC68010, return before data verification. If data is invalid, assert

DTACK

on the next clock cycle (case 4).

BERR BERR HALT

Table 5-6. and Negation Results

Negated on Rising

Conditions of Edge of State

Termination in

Table 4-4 Control Signal N N+2 Results—Next Cycle

Bus Error • or • Takes bus error trap.

BERR • or •

HALT

Rerun • or • Illegal sequence; usually traps to vector number 0.

BERR •

HALT

Rerun • Reruns the bus cycle.

BERR •

HALT

Normal • May lengthen next cycle.

BERR • or •

HALT

Normal • If next cycle is started, it will be terminated as a bus

BERR • or none error.

HALT

• = Signal is negated in this bus state.

5.7 ASYNCHRONOUS OPERATION

To achieve clock frequency independence at a system level, the bus can be operated in

an asynchronous manner. Asynchronous bus operation uses the bus handshake signals

to control the transfer of data. The handshake signals are (MC68008

AS, UDS, LDS, DS

only), (MC68EC000 only), and (only for M6800

DTACK, BERR, HALT, AVEC VPA

peripheral cycles). indicates the start of the bus cycle, and and signal

AS UDS, LDS, DS

valid data for a write cycle. After placing the requested data on the data bus (read cycle)

or latching the data (write cycle), the slave device (memory or peripheral) asserts DTACK

to terminate the bus cycle. If no device responds or if the access is invalid, external control

logic asserts or and to abort or retry the cycle. Figure 5-31 shows the

BERR, BERR HALT,

use of the bus handshake signals in a fully asynchronous read cycle. Figure 5-32 shows a

fully asynchronous write cycle.

ADDR

AS

R/W

UDS/LDS

DATA

DTACK Figure 5-31. Fully Asynchronous Read Cycle

5-32 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

ADDR

AS

R/W

UDS/LDS

DATA

DTACK Figure 5-32. Fully Asynchronous Write Cycle

In the asynchronous mode, the accessed device operates independently of the frequency

and phase of the system clock. For example, the MC68681 dual universal asynchronous

receiver/transmitter (DUART) does not require any clock-related information from the bus

master during a bus transfer. Asynchronous devices are designed to operate correctly

with processors at any clock frequency when relevant timing requirements are observed.

A device can use a clock at the same frequency as the system clock (e.g., 8, 10, or 12.5,

16, and 20MHz), but without a defined phase relationship to the system clock. This mode

of operation is pseudo-asynchronous; it increases performance by observing timing

parameters related to the system clock frequency without being completely synchronous

with that clock. A memory array designed to operate with a particular frequency processor

but not driven by the processor clock is a common example of a pseudo-asynchronous

device.

The designer of a fully asynchronous system can make no assumptions about address

setup time, which could be used to improve performance. With the system clock frequency

known, the slave device can be designed to decode the address bus before recognizing

an address strobe. Parameter #11 (refer to Section 10 Electrical Characteristics)

specifies the minimum time before address strobe during which the address is valid.

In a pseudo-asynchronous system, timing specifications allow to be asserted for a

DTACK

read cycle before the data from a slave device is valid. The length of time that DTACK

may precede data is specified as parameter #31. This parameter must be met to ensure

the validity of the data latched into the processor. No maximum time is specified from the

assertion of to the assertion of During this unlimited time, the processor

AS DTACK.

inserts wait cycles in one-clock-period increments until is recognized. Figure 5-33

DTACK

shows the important timing parameters for a pseudo-asynchronous read cycle.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-33

ADDR 11

AS 17

R/W

UDS/LDS 28

29

DATA 31

DTACK Figure 5-33. Pseudo-Asynchronous Read Cycle

During a write cycle, after the processor asserts but before driving the data bus, the

AS

processor drives R/W low. Parameter #55 specifies the minimum time between the

transition of R/W and the driving of the data bus, which is effectively the maximum turnoff

time for any device driving the data bus.

After the processor places valid data on the bus, it asserts the data strobe signal(s). A

data setup time, similar to the address setup time previously discussed, can be used to

improve performance. Parameter #29 is the minimum time a slave device can accept valid

data before recognizing a data strobe. The slave device asserts after it accepts

DTACK

the data. Parameter #25 is the minimum time after negation of the strobes during which

the valid data remains on the address bus. Parameter #28 is the maximum time between

the negation of the strobes by the processor and the negation of by the slave

DTACK

device. If remains asserted past the time specified by parameter #28, the

DTACK

processor may recognize it as being asserted early in the next bus cycle and may

terminate that cycle prematurely. Figure 5-34 shows the important timing specifications for

a pseudo-asynchronous write cycle.

5-34 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

ADDR 11

AS 20A

R/W 22

UDS/LDS 28

55 26 29

DATA

DTACK Figure 5-34. Pseudo-Asynchronous Write Cycle

In the MC68010, the signal can be delayed after the assertion of

BERR DTACK.

Specification #48 is the maximum time between assertion of and assertion of

DTACK

BERR. If this maximum delay is exceeded, operation of the processor may be erratic.

5.8 SYNCHRONOUS OPERATION

In some systems, external devices use the system clock to generate and other

DTACK

asynchronous input signals. This synchronous operation provides a closely coupled

design with maximum performance, appropriate for frequently accessed parts of the

system. For example, memory can operate in the synchronous mode, but peripheral

devices operate asynchronously. For a synchronous device, the designer uses explicit

timing information shown in Section 10 Electrical Characteristics. These specifications

define the state of all bus signals relative to a specific state of the processor clock.

The standard M68000 bus cycle consists of four clock periods (eight bus cycle states)

and, optionally, an integral number of clock cycles inserted as wait states. Wait states are

inserted as required to allow sufficient response time for the external device. The following

state-by-state description of the bus cycle differs from those descriptions in 5.1.1 READ

CYCLE and 5.1.2 WRITE CYCLE by including information about the important timing

parameters that apply in the bus cycle states.

STATE 0 The bus cycle starts in S0, during which the clock is high. At the rising edge

of S0, the function code for the access is driven externally. Parameter #6A

defines the delay from this rising edge until the function codes are valid.

Also, the R/W signal is driven high; parameter #18 defines the delay from

the same rising edge to the transition of R/W . The minimum value for

parameter #18 applies to a read cycle preceded by a write cycle; this value

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-35

is the maximum hold time for a low on R/W beyond the initiation of the read

cycle.

STATE 1 Entering S1, a low period of the clock, the address of the accessed device

is driven externally with an assertion delay defined by parameter #6.

STATE 2 On the rising edge of S2, a high period of the clock, is asserted. During

AS

a read cycle, and/or is also asserted at this time. Parameter

UDS, LDS, DS

#9 defines the assertion delay for these signals. For a write cycle, the R/W

signal is driven low with a delay defined by parameter #20.

STATE 3 On the falling edge of the clock entering S3, the data bus is driven out of

the high-impedance state with the data being written to the accessed

device (in a write cycle). Parameter #23 specifies the data assertion delay.

In a read cycle, no signal is altered in S3.

STATE 4 Entering the high clock period of S4, and/or is asserted

UDS, LDS, DS

(during a write cycle) on the rising edge of the clock. As in S2 for a read

cycle, parameter #9 defines the assertion delay from the rising edge of S4

for and/or In a read cycle, no signal is altered by the

UDS, LDS, DS.

processor during S4.

Until the falling edge of the clock at the end of S4 (beginning of S5), no

response from any external device except is acknowledged by the

RESET

processor. If either or is asserted before the falling edge of

DTACK BERR

S4 and satisfies the input setup time defined by parameter #47, the

processor enters S5 and the bus cycle continues. If either or

DTACK BERR

is asserted but without meeting the setup time defined by parameter #47,

the processor may recognize the signal and continue the bus cycle; the

result is unpredictable. If neither nor is asserted before the

DTACK BERR

next rise of clock, the bus cycle remains in S4, and wait states (complete

clock cycles) are inserted until one of the bus cycle termination is met.

STATE 5 S5 is a low period of the clock, during which the processor does not alter

any signal.

STATE 6 S6 is a high period of the clock, during which data for a read operation is

set up relative to the falling edge (entering S7). Parameter #27 defines the

minimum period by which the data must precede the falling edge. For a

write operation, the processor changes no signal during S6.

STATE 7 On the falling edge of the clock entering S7, the processor latches data

and negates and and/or during a read cycle. The hold

AS UDS, LDS, DS

time for these strobes from this falling edge is specified by parameter #12.

The hold time for data relative to the negation of and and/or

AS UDS, LDS,

is specified by parameter #29. For a write cycle, only and

DS AS UDS, LDS,

and/or are negated; timing parameter #12 also applies.

DS

5-36 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

On the rising edge of the clock, at the end of S7 (which may be the start of

S0 for the next bus cycle), the processor places the address bus in the

high-impedance state. During a write cycle, the processor also places the

data bus in the high-impedance state and drives R/W high. External logic

circuitry should respond to the negation of the and and/or

AS UDS, LDS, DS

by negating and/or Parameter #28 is the hold time for

DTACK BERR.

and parameter #30 is the hold time for

DTACK, BERR.

Figure 5-35 shows a synchronous read cycle and the important timing parameters that

apply. The timing for a synchronous read cycle, including relevant timing parameters, is

shown in Figure 5-36.

S0 S1 S2 S3 S4 S5 S6 S7 S0

CLOCK 6

ADDR 9

AS

UDS/LDS 18

R/W 47

DTACK 27

DATA Figure 5-35. Synchronous Read Cycle

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-37

S0 S1 S2 S3 S4 S5 S6 S7 S0

CLOCK 6 9

.

ADDR

AS

UDS/LDS 18

R/W 47

DTACK 23 53

DATA Figure 5-36. Synchronous Write Cycle

A key consideration when designing in a synchronous environment is the timing for the

assertion of and by an external device. To properly use external inputs, the

DTACK BERR

processor must synchronize these signals to the internal clock. The processor must

sample the external signal, which has no defined phase relationship to the CPU clock,

which may be changing at sampling time, and must determine whether to consider the

signal high or low during the succeeding clock period. Successful synchronization requires

that the internal machine receives a valid logic level (not a metastable signal), whether the

input is high, low, or in transition. Metastable signals propagating through synchronous

machines can produce unpredictable operation.

Figure 5-37 is a conceptual representation of the input synchronizers used by the M68000

Family processors. The input latches allow the input to propagate through to the output

when E is high. When low, E latches the input. The three latches require one cycle of CLK

to synchronize an external signal. The high-gain characteristics of the devices comprising

the latches quickly resolve a marginal signal into a valid state.

EXT INT

D Q D Q D Q

SIGNAL SIGNAL

G G G

CLK

CLK Figure 5-37. Input Synchronizers

5-38 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Parameter #47 of Section 10 Electrical Characteristics is the asynchronous input setup

time. Signals that meet parameter #47 are guaranteed to be recognized at the next falling

edge of the system clock. However, signals that do not meet parameter #47 are not

guaranteed to be recognized. In addition, if is recognized on a falling edge, valid

DTACK

data is latched into the processor (during a read cycle) on the next falling edge, provided

the data meets the setup time required (parameter #27). When parameter #27 has been

met, parameter #31 may be ignored. If is asserted with the required setup time

DTACK

before the falling edge of S4, no wait states are incurred, and the bus cycle runs at its

maximum speed of four clock periods.

The late in an MC68010 that is operating in a synchronous mode must meet setup

BERR

time parameter #27A. That is, when is asserted after must be

BERR DTACK, BERR

asserted before the falling edge of the clock, one clock cycle after is recognized.

DTACK

Violating this requirement may cause the MC68010 to operate erratically.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-39

5-40 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

SECTION 6

EXCEPTION PROCESSING

This section describes operations of the processor outside the normal processing

associated with the execution of instructions. The functions of the bits in the supervisor

portion of the status register are described: the supervisor/user bit, the trace enable bit,

and the interrupt priority mask. Finally, the sequence of memory references and actions

taken by the processor for exception conditions are described in detail.

The processor is always in one of three processing states: normal, exception, or halted.

The normal processing state is associated with instruction execution; the memory

references are to fetch instructions and operands and to store results. A special case of

the normal state is the stopped state, resulting from execution of a STOP instruction. In

this state, no further memory references are made.

An additional, special case of the normal state is the loop mode of the MC68010,

optionally entered when a test condition, decrement, and branch (DBcc) instruction is

executed. In the loop mode, only operand fetches occur. See Appendix A MC68010

Loop Mode Operation.

The exception processing state is associated with interrupts, trap instructions, tracing, and

other exceptional conditions. The exception may be internally generated by an instruction

or by an unusual condition arising during the execution of an instruction. Externally,

exception processing can be forced by an interrupt, by a bus error, or by a reset.

Exception processing provides an efficient context switch so that the processor can

handle unusual conditions.

The halted processing state is an indication of catastrophic hardware failure. For example,

if during the exception processing of a bus error another bus error occurs, the processor

assumes the system is unusable and halts. Only an external reset can restart a halted

processor. Note that a processor in the stopped state is not in the halted state, nor vice

versa.

6.1 PRIVILEGE MODES

The processor operates in one of two levels of privilege: the supervisor mode or the user

mode. The privilege mode determines which operations are legal. The mode is optionally

used by an external memory management device to control and translate accesses. The

mode is also used to choose between the supervisor stack pointer (SSP) and the user

stack pointer (USP) in instruction references.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-1

The privilege mode is a mechanism for providing security in a computer system. Programs

should access only their own code and data areas and should be restricted from

accessing information that they do not need and must not modify. The operating system

executes in the supervisor mode, allowing it to access all resources required to perform

the overhead tasks for the user mode programs. Most programs execute in user mode, in

which the accesses are controlled and the effects on other parts of the system are limited.

6.1.1 Supervisor Mode

The supervisor mode has the higher level of privilege. The mode of the processor is

determined by the S bit of the status register; if the S bit is set, the processor is in the

supervisor mode. All instructions can be executed in the supervisor mode. The bus cycles

generated by instructions executed in the supervisor mode are classified as supervisor

references. While the processor is in the supervisor mode, those instructions that use

either the system stack pointer implicitly or address register seven explicitly access the

SSP.

6.1.2 User Mode

The user mode has the lower level of privilege. If the S bit of the status register is clear,

the processor is executing instructions in the user mode.

Most instructions execute identically in either mode. However, some instructions having

important system effects are designated privileged. For example, user programs are not

permitted to execute the STOP instruction or the RESET instruction. To ensure that a user

program cannot enter the supervisor mode except in a controlled manner, the instructions

that modify the entire status register are privileged. To aid in debugging systems software,

the move to user stack pointer (MOVE to USP) and move from user stack pointer (MOVE

from USP) instructions are privileged. NOTE

To implement virtual machine concepts in the MC68010, the

move from status register (MOVE from SR), move to/from

control register (MOVEC), and move alternate address space

(MOVES) instructions are also privileged.

The bus cycles generated by an instruction executed in user mode are classified as user

references. Classifying a bus cycle as a user reference allows an external memory

management device to translate the addresses of and control access to protected portions

of the address space. While the processor is in the user mode, those instructions that use

either the system stack pointer implicitly or address register seven explicitly access the

USP.

6.1.3 Privilege Mode Changes

Once the processor is in the user mode and executing instructions, only exception

processing can change the privilege mode. During exception processing, the current state

of the S bit of the status register is saved, and the S bit is set, putting the processor in the

6-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

supervisor mode. Therefore, when instruction execution resumes at the address specified

to process the exception, the processor is in the supervisor privilege mode.

NOTE

The transition from supervisor to user mode can be

accomplished by any of four instructions: return from exception

(RTE) (MC68010 only), move to status register (MOVE to SR),

AND immediate to status register (ANDI to SR), and exclusive

OR immediate to status register (EORI to SR). The RTE

instruction in the MC68010 fetches the new status register and

program counter from the supervisor stack and loads each into

its respective register. Next, it begins the instruction fetch at

the new program counter address in the privilege mode

determined by the S bit of the new contents of the status

register.

The MOVE to SR, ANDI to SR, and EORI to SR instructions fetch all operands in the

supervisor mode, perform the appropriate update to the status register, and then fetch the

next instruction at the next sequential program counter address in the privilege mode

determined by the new S bit.

6.1.4 Reference Classification

When the processor makes a reference, it classifies the reference according to the

encoding of the three function code output lines. This classification allows external

translation of addresses, control of access, and differentiation of special processor states,

such as CPU space (used by interrupt acknowledge cycles). Table 6-1 lists the

classification of references.

Table 6-1. Reference Classification

Function Code Output

FC2 FC1 FC0 Address Space

0 0 0 (Undefined, Reserved)*

0 0 1 User Data

0 1 0 User Program

0 1 1 (Undefined, Reserved)*

1 0 0 (Undefined, Reserved)*

1 0 1 Supervisor Data

1 1 0 Supervisor Program

1 1 1 CPU Space

*Address space 3 is reserved for user definition, while 0 and

4 are reserved for future use by Motorola.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-3

6.2 EXCEPTION PROCESSING

The processing of an exception occurs in four steps, with variations for different exception

causes:

1. Make a temporary copy of the status register and set the status register for

exception processing.

2. Obtain the exception vector.

3. Save the current processor context.

4. Obtain a new context and resume instruction processing.

6.2.1 Exception Vectors

An exception vector is a memory location from which the processor fetches the address of

a routine to handle an exception. Each exception type requires a handler routine and a

unique vector. All exception vectors are two words in length (see Figure 6-1), except for

the reset vector, which is four words long. All exception vectors reside in the supervisor

data space, except for the reset vector, which is in the supervisor program space. A vector

number is an 8-bit number that is multiplied by four to obtain the offset of an exception

vector. Vector numbers are generated internally or externally, depending on the cause of

the exception. For interrupts, during the interrupt acknowledge bus cycle, a peripheral

provides an 8-bit vector number (see Figure 6-2) to the processor on data bus lines D7–

D0.

The processor forms the vector offset by left-shifting the vector number two bit positions

and zero-filling the upper-order bits to obtain a 32-bit long-word vector offset. In the

MC68000, the MC68HC000, MC68HC001, MC68EC000, and the MC68008, this offset is

used as the absolute address to obtain the exception vector itself, which is shown in

Figure 6-3. NOTE

In the MC68010, the vector offset is added to the 32-bit vector

base register (VBR) to obtain the 32-bit absolute address of

the exception vector (see Figure 6-4). Since the VBR is set to

zero upon reset, the MC68010 functions identically to the

MC68000, MC68HC000, MC68HC001, MC68EC000, and

MC68008 until the VBR is changed via the move control

register MOVEC instruction.

EVEN BYTE (A0=0) EVEN BYTE (A0=0)

WORD 0 NEW PROGRAM COUNTER (HIGH) A1=0

WORD 1 NEW PROGRAM COUNTER (LOW) A1=1

Figure 6-1. Exception Vector Format

6-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

D15 D8 D7 D0

IGNORED v7 v6 v5 v4 v3 v2 v1 v0

Where:

v7 is the MSB of the vector number

v0 is the LSB of the vector number

Figure 6-2. Peripheral Vector Number Format

A31 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

ALL ZEROES v7 v6 v5 v4 v3 v2 v1 v0 0 0

Figure 6-3. Address Translated from 8-Bit Vector Number

(MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008)

31 0

CONTENTS OF VECTOR BASE REGISTER

31 0

10 +

ALL ZEROES v7 v6 v5 v4 v3 v2 v1 v0 0 0 EXCEPTION VECTOR

ADDRESS

Figure 6-4. Exception Vector Address Calculation (MC68010)

The actual address on the address bus is truncated to the number of address bits

available on the bus of the particular implementation of the M68000 architecture. In all

processors except the MC68008, this is 24 address bits. (A0 is implicitly encoded in the

data strobes.) In the MC68008, the address is 20 or 22 bits in length. The memory map for

exception vectors is shown in Table 6-2.

The vector table, Table 6-2, is 512 words long (1024 bytes), starting at address 0

(decimal) and proceeding through address 1023 (decimal). The vector table provides 255

unique vectors, some of which are reserved for trap and other system function vectors. Of

the 255, 192 are reserved for user interrupt vectors. However, the first 64 entries are not

protected, so user interrupt vectors may overlap at the discretion of the systems designer.

6.2.2 Kinds of Exceptions

Exceptions can be generated by either internal or external causes. The externally

generated exceptions are the interrupts, the bus error, and reset. The interrupts are

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-5

requests from peripheral devices for processor action; the bus error and reset inputs are

used for access control and processor restart. The internal exceptions are generated by

instructions, address errors, or tracing. The trap (TRAP), trap on overflow (TRAPV), check

register against bounds (CHK), and divide (DIV) instructions can generate exceptions as

part of their instruction execution. In addition, illegal instructions, word fetches from odd

addresses, and privilege violations cause exceptions. Tracing is similar to a very high

priority, internally generated interrupt following each instruction.

6-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 6-2. Exception Vector Assignment

Vectors Numbers Address 6

Hex Decimal Dec Hex Space Assignment

SSP2

0 0 0 000 SP Reset: Initial 2

1 1 4 004 SP Reset: Initial PC

2 2 8 008 SD Bus Error

3 3 12 00C SD Address Error

4 4 16 010 SD Illegal Instruction

5 5 20 014 SD Zero Divide

6 6 24 018 SD CHK Instruction

7 7 28 01C SD TRAPV Instruction

8 8 32 020 SD Privilege Violation

9 9 36 024 SD Trace

A 10 40 028 SD Line 1010 Emulator

B 11 44 02C SD Line 1111 Emulator

121

C 48 030 SD (Unassigned, Reserved)

131

D 52 034 SD (Unassigned, Reserved)

5

E 14 56 038 SD Format Error

F 15 60 03C SD Uninitialized Interrupt Vector

16–231

10–17 64 040 SD (Unassigned, Reserved)

92 05C — 3

18 24 96 060 SD Spurious Interrupt

19 25 100 064 SD Level 1 Interrupt Autovector

1A 26 104 068 SD Level 2 Interrupt Autovector

1B 27 108 06C SD Level 3 Interrupt Autovector

1C 28 112 070 SD Level 4 Interrupt Autovector

1D 29 116 074 SD Level 5 Interrupt Autovector

1E 30 120 078 SD Level 6 Interrupt Autovector

1F 31 124 07C SD Level 7 Interrupt Autovector

Vectors4

20–2F 32–47 128 080 SD TRAP Instruction

188 0BC —

48–631

30–3F 192 0C0 SD (Unassigned, Reserved)

255 0FF —

40–FF 64–255 256 100 SD User Interrupt Vectors

1020 3FC —

NOTES:

1. Vector numbers 12, 13, 16–23, and 48–63 are reserved for future

enhancements by Motorola. No user peripheral devices should be

assigned these numbers.

2. Reset vector (0) requires four words, unlike the other vectors which only

require two words, and is located in the supervisor program space.

3. The spurious interrupt vector is taken when there is a bus error

indication during interrupt processing.

4. TRAP #n uses vector number 32+ n.

5. MC68010 only. This vector is unassigned, reserved on the MC68000

and MC68008.

6. SP denotes supervisor program space, and SD denotes

supervisor data space.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-7

6.2.3 Multiple Exceptions

These paragraphs describe the processing that occurs when multiple exceptions arise

simultaneously. Exceptions can be grouped by their occurrence and priority. The group 0

exceptions are reset, bus error, and address error. These exceptions cause the instruction

currently being executed to abort and the exception processing to commence within two

clock cycles. The group 1 exceptions are trace and interrupt, privilege violations, and

illegal instructions. Trace and interrupt exceptions allow the current instruction to execute

to completion, but pre-empt the execution of the next instruction by forcing exception

processing to occur. A privilege-violating instruction or an illegal instruction is detected

when it is the next instruction to be executed. The group 2 exceptions occur as part of the

normal processing of instructions. The TRAP, TRAPV, CHK, and zero divide exceptions

are in this group. For these exceptions, the normal execution of an instruction may lead to

exception processing.

Group 0 exceptions have highest priority, whereas group 2 exceptions have lowest

priority. Within group 0, reset has highest priority, followed by address error and then bus

error. Within group 1, trace has priority over external interrupts, which in turn takes priority

over illegal instruction and privilege violation. Since only one instruction can be executed

at a time, no priority relationship applies within group 2.

The priority relationship between two exceptions determines which is taken, or taken first,

if the conditions for both arise simultaneously. Therefore, if a bus error occurs during a

TRAP instruction, the bus error takes precedence, and the TRAP instruction processing is

aborted. In another example, if an interrupt request occurs during the execution of an

instruction while the T bit is asserted, the trace exception has priority and is processed

first. Before instruction execution resumes, however, the interrupt exception is also

processed, and instruction processing finally commences in the interrupt handler routine.

A summary of exception grouping and priority is given in Table 6-3.

As a general rule, the lower the priority of an exception, the sooner the handler routine for

that exception executes. For example, if simultaneous trap, trace, and interrupt exceptions

are pending, the exception processing for the trap occurs first, followed immediately by

exception processing for the trace and then for the interrupt. When the processor resumes

normal instruction execution, it is in the interrupt handler, which returns to the trace

handler, which returns to the trap execution handler. This rule does not apply to the reset

exception; its handler is executed first even though it has the highest priority, because the

reset operation clears all other exceptions.

6-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 6-3. Exception Grouping and Priority

Group Exception Processing

Exception Processing Begins within Two Clock Cycles

0 Reset

Address Error

Bus Error Exception Processing Begins before the Next Instruction

1 Trace

Interrupt

Illegal

Privilege Exception Processing Is Started by Normal Instruction Execution

2 TRAP, TRAPV,

CHK

Zero Divide

6.2.4 Exception Stack Frames

Exception processing saves the most volatile portion of the current processor context on

the top of the supervisor stack. This context is organized in a format called the exception

stack frame. Although this information varies with the particular processor and type of

exception, it always includes the status register and program counter of the processor

when the exception occurred.

The amount and type of information saved on the stack are determined by the processor

type and exception type. Exceptions are grouped by type according to priority of the

exception.

Of the group 0 exceptions, the reset exception does not stack any information. The

information stacked by a bus error or address error exception in the MC68000,

MC68HC000, MC68HC001, MC68EC000, or MC68008 is described in 6.3.9.1 Bus Error

and shown in Figure 6-7.

The MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008 group 1 and 2

exception stack frame is shown in Figure 6-5. Only the program counter and status

register are saved. The program counter points to the next instruction to be executed after

exception processing.

The MC68010 exception stack frame is shown in Figure 5-6. The number of words

actually stacked depends on the exception type. Group 0 exceptions (except reset) stack

29 words and group 1 and 2 exceptions stack four words. To support generic exception

handlers, the processor also places the vector offset in the exception stack frame. The

format code field allows the return from exception (RTE) instruction to identify what

information is on the stack so that it can be properly restored. Table 6-4 lists the MC68010

format codes. Although some formats are specific to a particular M68000 Family

processor, the format 0000 is always legal and indicates that just the first four words of the

frame are present.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-9

EVEN BYTE ODD BYTE

7 0 7 0

15 0 HIGHER

ADDRESS

STATUS REGISTER

SSP PROGRAM COUNTER HIGH

PROGRAM COUNTER LOW

Figure 6-5. Group 1 and 2 Exception Stack Frame

(MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008)

15 0 HIGHER

ADDRESS

STATUS REGISTER

SP PROGRAM COUNTER HIGH

PROGRAM COUNTER LOW

FORMAT VECTOR OFFSET

OTHER INFORMATION

DEPENDING ON EXCEPTION

Figure 6-6. MC68010 Stack Frame

6-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 6-4. MC68010 Format Codes

Format Code Stacked Information

0000 Short Format (4 Words)

1000 Long Format (29 Words)

All Others Unassigned, Reserved

6.2.5 Exception Processing Sequence

In the first step of exception processing, an internal copy is made of the status register.

After the copy is made, the S bit of the status register is set, putting the processor into the

supervisor mode. Also, the T bit is cleared, which allows the exception handler to execute

unhindered by tracing. For the reset and interrupt exceptions, the interrupt priority mask is

also updated appropriately.

In the second step, the vector number of the exception is determined. For interrupts, the

vector number is obtained by a processor bus cycle classified as an interrupt acknowledge

cycle. For all other exceptions, internal logic provides the vector number. This vector

number is then used to calculate the address of the exception vector.

The third step, except for the reset exception, is to save the current processor status. (The

reset exception does not save the context and skips this step.) The current program

counter value and the saved copy of the status register are stacked using the SSP. The

stacked program counter value usually points to the next unexecuted instruction.

However, for bus error and address error, the value stacked for the program counter is

unpredictable and may be incremented from the address of the instruction that caused the

error. Group 1 and 2 exceptions use a short format exception stack frame (format = 0000

on the MC68010). Additional information defining the current context is stacked for the bus

error and address error exceptions.

The last step is the same for all exceptions. The new program counter value is fetched

from the exception vector. The processor then resumes instruction execution. The

instruction at the address in the exception vector is fetched, and normal instruction

decoding and execution is started.

6.3 PROCESSING OF SPECIFIC EXCEPTIONS

The exceptions are classified according to their sources, and each type is processed

differently. The following paragraphs describe in detail the types of exceptions and the

processing of each type.

6.3.1 Reset

The reset exception corresponds to the highest exception level. The processing of the

reset exception is performed for system initiation and recovery from catastrophic failure.

Any processing in progress at the time of the reset is aborted and cannot be recovered.

The processor is forced into the supervisor state, and the trace state is forced off. The

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-11

interrupt priority mask is set at level 7. In the MC68010, the VBR is forced to zero. The

vector number is internally generated to reference the reset exception vector at location 0

in the supervisor program space. Because no assumptions can be made about the validity

of register contents, in particular the SSP, neither the program counter nor the status

register is saved. The address in the first two words of the reset exception vector is

fetched as the initial SSP, and the address in the last two words of the reset exception

vector is fetched as the initial program counter. Finally, instruction execution is started at

the address in the program counter. The initial program counter should point to the power-

up/restart code.

The RESET instruction does not cause a reset exception; it asserts the signal to

RESET

reset external devices, which allows the software to reset the system to a known state and

continue processing with the next instruction.

6.3.2 Interrupts

Seven levels of interrupt priorities are provided, numbered from 1–7. All seven levels are

available except for the 48-pin version for the MC68008.

NOTE

The MC68008 48-pin version supports only three interrupt

levels: 2, 5, and 7. Level 7 has the highest priority.

Devices can be chained externally within interrupt priority levels, allowing an unlimited

number of peripheral devices to interrupt the processor. The status register contains a 3-

bit mask indicating the current interrupt priority, and interrupts are inhibited for all priority

levels less than or equal to the current priority.

An interrupt request is made to the processor by encoding the interrupt request levels 1–7

on the three interrupt request lines; all lines negated indicates no interrupt request.

Interrupt requests arriving at the processor do not force immediate exception processing,

but the requests are made pending. Pending interrupts are detected between instruction

executions. If the priority of the pending interrupt is lower than or equal to the current

processor priority, execution continues with the next instruction, and the interrupt

exception processing is postponed until the priority of the pending interrupt becomes

greater than the current processor priority.

If the priority of the pending interrupt is greater than the current processor priority, the

exception processing sequence is started. A copy of the status register is saved; the

privilege mode is set to supervisor mode; tracing is suppressed; and the processor priority

level is set to the level of the interrupt being acknowledged. The processor fetches the

vector number from the interrupting device by executing an interrupt acknowledge cycle,

which displays the level number of the interrupt being acknowledged on the address bus.

If external logic requests an automatic vector, the processor internally generates a vector

number corresponding to the interrupt level number. If external logic indicates a bus error,

the interrupt is considered spurious, and the generated vector number references the

spurious interrupt vector. The processor then proceeds with the usual exception

processing, saving the format/offset word (MC68010 only), program counter, and status

6-12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

register on the supervisor stack. The offset value in the format/offset word on the

MC68010 is the vector number multiplied by four. The format is all zeros. The saved value

of the program counter is the address of the instruction that would have been executed

had the interrupt not been taken. The appropriate interrupt vector is fetched and loaded

into the program counter, and normal instruction execution commences in the interrupt

handling routine. Priority level 7 is a special case. Level 7 interrupts cannot be inhibited by

the interrupt priority mask, thus providing a "nonmaskable interrupt" capability. An interrupt

is generated each time the interrupt request level changes from some lower level to level

7. A level 7 interrupt may still be caused by the level comparison if the request level is a 7

and the processor priority is set to a lower level by an instruction.

6.3.3 Uninitialized Interrupt

An interrupting device provides an M68000 interrupt vector number and asserts data

transfer acknowledge (DTACK), or asserts valid peripheral address (VPA), or auto vector

(AVEC), or bus error (BERR) during an interrupt acknowledge cycle by the MC68000. If

the vector register has not been initialized, the responding M68000 Family peripheral

provides vector number 15, the uninitialized interrupt vector. This response conforms to a

uniform way to recover from a programming error.

6.3.4 Spurious Interrupt

During the interrupt acknowledge cycle, if no device responds by asserting or

DTACK

should be asserted to terminate the vector acquisition. The processor

AVEC, VPA, BERR

separates the processing of this error from bus error by forming a short format exception

stack and fetching the spurious interrupt vector instead of the bus error vector. The

processor then proceeds with the usual exception processing.

6.3.5 Instruction Traps

Traps are exceptions caused by instructions; they occur when a processor recognizes an

abnormal condition during instruction execution or when an instruction is executed that

normally traps during execution.

Exception processing for traps is straightforward. The status register is copied; the

supervisor mode is entered; and tracing is turned off. The vector number is internally

generated; for the TRAP instruction, part of the vector number comes from the instruction

itself. The format/offset word (MC68010 only), the program counter, and the copy of the

status register are saved on the supervisor stack. The offset value in the format/offset

word on the MC68010 is the vector number multiplied by four. The saved value of the

program counter is the address of the instruction following the instruction that generated

the trap. Finally, instruction execution commences at the address in the exception vector.

Some instructions are used specifically to generate traps. The TRAP instruction always

forces an exception and is useful for implementing system calls for user programs. The

TRAPV and CHK instructions force an exception if the user program detects a run-time

error, which may be an arithmetic overflow or a subscript out of bounds.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-13

A signed divide (DIVS) or unsigned divide (DIVU) instruction forces an exception if a

division operation is attempted with a divisor of zero.

6.3.6 Illegal and Unimplemented Instructions

Illegal instruction is the term used to refer to any of the word bit patterns that do not match

the bit pattern of the first word of a legal M68000 instruction. If such an instruction is

fetched, an illegal instruction exception occurs. Motorola reserves the right to define

instructions using the opcodes of any of the illegal instructions. Three bit patterns always

force an illegal instruction trap on all M68000-Family-compatible microprocessors. The

patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are

reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer

use (as the take illegal instruction trap (ILLEGAL) instruction).

NOTE

In addition to the previously defined illegal instruction opcodes,

the MC68010 defines eight breakpoint (BKPT) instructions with

the bit patterns $4848–$484F. These instructions cause the

processor to enter illegal instruction exception processing as

usual. However, a breakpoint acknowledge bus cycle, in which

the function code lines (FC2–FC0) are high and the address

lines are all low, is also executed before the stacking

operations are performed. The processor does not accept or

send any data during this cycle. Whether the breakpoint

acknowledge cycle is terminated with a or

DTACK, BERR, VPA

signal, the processor continues with the illegal instruction

processing. The purpose of this cycle is to provide a software

breakpoint that signals to external hardware when it is

executed.

Word patterns with bits 15–12 equaling 1010 or 1111 are distinguished as unimplemented

instructions, and separate exception vectors are assigned to these patterns to permit

efficient emulation. Opcodes beginning with bit patterns equaling 1111 (line F) are

implemented in the MC68020 and beyond as coprocessor instructions. These separate

vectors allow the operating system to emulate unimplemented instructions in software.

Exception processing for illegal instructions is similar to that for traps. After the instruction

is fetched and decoding is attempted, the processor determines that execution of an illegal

instruction is being attempted and starts exception processing. The exception stack frame

for group 2 is then pushed on the supervisor stack, and the illegal instruction vector is

fetched.

6-14 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

6.3.7 Privilege Violations

To provide system security, various instructions are privileged. An attempt to execute one

of the privileged instructions while in the user mode causes an exception. The privileged

instructions are as follows:

AND Immediate to SR MOVE USP

EOR Immediate to SR OR Immediate to SR

MOVE to SR (68010 only) RESET

MOVE from SR (68010 only) RTE

MOVEC (68010 only) STOP

MOVES (68010 only)

Exception processing for privilege violations is nearly identical to that for illegal

instructions. After the instruction is fetched and decoded and the processor determines

that a privilege violation is being attempted, the processor starts exception processing.

The status register is copied; the supervisor mode is entered; and tracing is turned off.

The vector number is generated to reference the privilege violation vector, and the current

program counter and the copy of the status register are saved on the supervisor stack. If

the processor is an MC68010, the format/offset word is also saved. The saved value of

the program counter is the address of the first word of the instruction causing the privilege

violation. Finally, instruction execution commences at the address in the privilege violation

exception vector.

6.3.8 Tracing

To aid in program development, the M68000 Family includes a facility to allow tracing

following each instruction. When tracing is enabled, an exception is forced after each

instruction is executed. Thus, a debugging program can monitor the execution of the

program under test.

The trace facility is controlled by the T bit in the supervisor portion of the status register. If

the T bit is cleared (off), tracing is disabled and instruction execution proceeds from

instruction to instruction as normal. If the T bit is set (on) at the beginning of the execution

of an instruction, a trace exception is generated after the instruction is completed. If the

instruction is not executed because an interrupt is taken or because the instruction is

illegal or privileged, the trace exception does not occur. The trace exception also does not

occur if the instruction is aborted by a reset, bus error, or address error exception. If the

instruction is executed and an interrupt is pending on completion, the trace exception is

processed before the interrupt exception. During the execution of the instruction, if an

exception is forced by that instruction, the exception processing for the instruction

exception occurs before that of the trace exception.

As an extreme illustration of these rules, consider the arrival of an interrupt during the

execution of a TRAP instruction while tracing is enabled. First, the trap exception is

processed, then the trace exception, and finally the interrupt exception. Instruction

execution resumes in the interrupt handler routine.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-15

After the execution of the instruction is complete and before the start of the next

instruction, exception processing for a trace begins. A copy is made of the status register.

The transition to supervisor mode is made, and the T bit of the status register is turned off,

disabling further tracing. The vector number is generated to reference the trace exception

vector, and the current program counter and the copy of the status register are saved on

the supervisor stack. On the MC68010, the format/offset word is also saved on the

supervisor stack. The saved value of the program counter is the address of the next

instruction. Instruction execution commences at the address contained in the trace

exception vector.

6.3.9 Bus Error

A bus error exception occurs when the external logic requests that a bus error be

processed by an exception. The current bus cycle is aborted. The current processor

activity, whether instruction or exception processing, is terminated, and the processor

immediately begins exception processing. The bus error facility is identical on the all

processors; however, the stack frame produced on the MC68010 contains more

information. The larger stack frame supports instruction continuation, which supports

virtual memory on the MC68010 processor.

6.3.9.1 BUS ERROR. Exception processing for a bus error follows the usual sequence of

steps. The status register is copied, the supervisor mode is entered, and tracing is turned

off. The vector number is generated to refer to the bus error vector. Since the processor is

fetching the instruction or an operand when the error occurs, the context of the processor

is more detailed. To save more of this context, additional information is saved on the

supervisor stack. The program counter and the copy of the status register are saved. The

value saved for the program counter is advanced 2–10 bytes beyond the address of the

first word of the instruction that made the reference causing the bus error. If the bus error

occurred during the fetch of the next instruction, the saved program counter has a value in

the vicinity of the current instruction, even if the current instruction is a branch, a jump, or

a return instruction. In addition to the usual information, the processor saves its internal

copy of the first word of the instruction being processed and the address being accessed

by the aborted bus cycle. Specific information about the access is also saved: type of

access (read or write), processor activity (processing an instruction), and function code

outputs when the bus error occurred. The processor is processing an instruction if it is in

the normal state or processing a group 2 exception; the processor is not processing an

instruction if it is processing a group 0 or a group 1 exception. Figure 6-7 illustrates how

this information is organized on the supervisor stack. If a bus error occurs during the last

step of exception processing, while either reading the exception vector or fetching the

instruction, the value of the program counter is the address of the exception vector.

Although this information is not generally sufficient to effect full recovery from the bus

error, it does allow software diagnosis. Finally, the processor commences instruction

processing at the address in the vector. It is the responsibility of the error handler routine

to clean up the stack and determine where to continue execution.

If a bus error occurs during the exception processing for a bus error, an address error, or

a reset, the processor halts and all processing ceases. This halt simplifies the detection of

a catastrophic system failure, since the processor removes itself from the system to

6-16 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

protect memory contents from erroneous accesses. Only an external reset operation can

restart a halted processor.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LOWER ADDRESS R/W I/N FUNCTION CODE

HIGH

ACCESS ADDRESS LOW

INSTRUCTION REGISTER

STATUS REGISTER

HIGH

PROGRAM COUNTER LOW

R/W (Read/Write): Write=0, Read=1. I/N (Instruction/Not): Instruction=0, Not=1

Figure 6-7. Supervisor Stack Order for Bus or Address Error Exception

6.3.9.2 BUS ERROR (MC68010). Exception processing for a bus error follows a slightly

different sequence than the sequence for group 1 and 2 exceptions. In addition to the four

steps executed during exception processing for all other exceptions, 22 words of

additional information are placed on the stack. This additional information describes the

internal state of the processor at the time of the bus error and is reloaded by the RTE

instruction to continue the instruction that caused the error. Figure 6-8 shows the order of

the stacked information.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-17

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SP STATUS REGISTER

PROGRAM COUNTER (HIGH)

PROGRAM COUNTER (LOW)

1000 VECTOR OFFSET

SPECIAL STATUS WORD

FAULT ADDRESS (HIGH)

FAULT ADDRESS (LOW)

UNUSED, RESERVED

DATA OUTPUT BUFFER

UNUSED, RESERVED

DATA INPUT BUFFER

UNUSED, RESERVED

INSTRUCTION INPUT BUFFER

VERSION

NUMBER

INTERNAL INFORMATION, 16 WORDS

NOTE: The stack pointer is decremented by 29 words, although only 26

words of information are actually written to memory. The three

additional words are reserved for future use by Motorola.

.

Figure 6-8. Exception Stack Order (Bus and Address Error)

The value of the saved program counter does not necessarily point to the instruction that

was executing when the bus error occurred, but may be advanced by as many as five

words. This incrementing is caused by the prefetch mechanism on the MC68010 that

always fetches a new instruction word as each previously fetched instruction word is used.

However, enough information is placed on the stack for the bus error exception handler to

determine why the bus fault occurred. This additional information includes the address

being accessed, the function codes for the access, whether it was a read or a write

access, and the internal register included in the transfer. The fault address can be used by

an operating system to determine what virtual memory location is needed so that the

requested data can be brought into physical memory. The RTE instruction is used to

reload the internal state of the processor at the time of the fault. The faulted bus cycle is

then rerun, and the suspended instruction is completed. If the faulted bus cycle is a read-

modify-write, the entire cycle is rerun, whether the fault occurred during the read or the

write operation.

An alternate method of handling a bus error is to complete the faulted access in software.

Using this method requires the special status word, the instruction input buffer, the data

input buffer, and the data output buffer image. The format of the special status word is

6-18 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

shown in Figure 6-9. If the bus cycle is a read, the data at the fault address should be

written to the images of the data input buffer, instruction input buffer, or both according to

* In addition, for read-modify-write cycles,

the data fetch (DF) and instruction fetch (IF) bits.

the status register image must be properly set to reflect the read data if the fault occurred

during the read portion of the cycle and the write operation (i.e., setting the most

significant bit of the memory location) must also be performed. These operations are

required because the entire read-modify-write cycle is assumed to have been completed

by software. Once the cycle has been completed by software, the rerun (RR) bit in the

special status word is set to indicate to the processor that it should not rerun the cycle

when the RTE instruction is executed. If the RR bit is set when an RTE instruction

executes, the MC68010 reads all the information from the stack, as usual.

15 14 13 12 11 10 9 8 7 3 2 0

RR * IF DF RM HB BY RW * FC2–FC0

RR — Rerun flag; 0=processor rerun (default), 1=software rerun

IF — Instruction fetch to the instruction input buffer

DF — Data fetch to the data input buffer

RM — Read-modify-write cycle

HB — High-byte transfer from the data output buffer or to the data input buffer

BY — Byte-transfer flag; HB selects the high or low byte of the transfer register. If BY is clear, the transfer is word.

RW — Read/write flag; 0=write, 1=read

FC — The function code used during the faulted access

* — These bits are reserved for future use by Motorola and will be zero when written by the MC68010.

Figure 6-9. Special Status Word Format

6.3.10 Address Error

An address error exception occurs when the processor attempts to access a word or long-

word operand or an instruction at an odd address. An address error is similar to an

internally generated bus error. The bus cycle is aborted, and the processor ceases current

processing and begins exception processing. The exception processing sequence is the

same as that for a bus error, including the information to be stacked, except that the

vector number refers to the address error vector. Likewise, if an address error occurs

during the exception processing for a bus error, address error, or reset, the processor is

halted.

On the MC68010, the address error exception stacks the same information stacked by a

bus error exception. Therefore, the RTE instruction can be used to continue execution of

the suspended instruction. However, if the RR flag is not set, the fault address is used

when the cycle is retried, and another address error exception occurs. Therefore, the user

must be certain that the proper corrections have been made to the stack image and user

registers before attempting to continue the instruction. With proper software handling, the

address error exception handler could emulate word or long-word accesses to odd

addresses if desired.

* If the faulted access was a byte operation, the data should be moved from or to the least significant byte of

the data output or input buffer images, unless the high-byte transfer (HB) bit is set. This condition occurs if a

MOVEP instruction caused the fault during transfer of bits 8–15 of a word or long word or bits 24–31 of a

long word.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-19

6.4 RETURN FROM EXCEPTION (MC68010)

In addition to returning from any exception handler routine on the MC68010, the RTE

instruction resumes the execution of a suspended instruction by returning to the normal

processing state after restoring all of the temporary register and control information stored

during a bus error. For the RTE instruction to execute properly, the stack must contain

valid and accessible data. The RTE instruction checks for data validity in two ways. First,

the format/offset word is checked for a valid stack format code. Second, if the format code

indicates the long stack format, the validity of the long stack data is checked as it is loaded

into the processor. In addition, the data is checked for accessibility when the processor

starts reading the long data. Because of these checks, the RTE instruction executes as

follows:

1. Determine the stack format. This step is the same for any stack format and consists

of reading the status register, program counter, and format/offset word. If the format

code indicates a short stack format, execution continues at the new program counter

address. If the format code is not an MC68010-defined stack format code, exception

processing starts for a format error.

2. Determine data validity. For a long-stack format, the MC68010 begins to read the

remaining stack data, checking for validity of the data. The only word checked for

validity is the first of the 16 internal information words (SP + 26) shown in Figure 5-8.

This word contains a processor version number (in bits 10–13) and proprietary

internal information that must match the version number of the MC68010 attempting

to read the data. This validity check is used to ensure that the data is properly

interpreted by the RTE instruction. If the version number is incorrect for this

processor, the RTE instruction is aborted and exception processing begins for a

format error exception. Since the stack pointer is not updated until the RTE

instruction has successfully read all the stack data, a format error occurring at this

point does not stack new data over the previous bus error stack information.

3. Determine data accessibility. If the long-stack data is valid, the MC68010 performs a

read from the last word (SP + 56) of the long stack to determine data accessibility. If

this read is terminated normally, the processor assumes that the remaining words on

the stack frame are also accessible. If a bus error is signaled before or during this

read, a bus error exception is taken. After this read, the processor must be able to

load the remaining data without receiving a bus error; therefore, if a bus error occurs

on any of the remaining stack reads, the error becomes a double bus fault, and the

MC68010 enters the halted state.

6-20 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

SECTION 7

8-BIT INSTRUCTION EXECUTION TIMES

This section contains listings of the instruction execution times in terms of external clock

(CLK) periods for the MC68008 and MC68HC001/MC68EC000 in 8-bit mode. In this data,

it is assumed that both memory read and write cycles consist of four clock periods. A

longer memory cycle causes the generation of wait states that must be added to the total

instruction times.

The number of bus read and write cycles for each instruction is also included with the

timing data. This data is shown as n(r/w)

where:

n is the total number of clock periods

r is the number of read cycles

w is the number of write cycles

For example, a timing number shown as 18(3/1) means that 18 clock periods are required

to execute the instruction. Of the 18 clock periods, 12 are used for the three read cycles

(four periods per cycle). Four additional clock periods are used for the single write cycle,

for a total of 16 clock periods. The bus is idle for two clock periods during which the

processor completes the internal operations required for the instruction.

NOTE

The total number of clock periods (n) includes instruction fetch

and all applicable operand fetches and stores.

7.1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES

Table 7-1 lists the numbers of clock periods required to compute the effective addresses

for instructions. The totals include fetching any extension words, computing the address,

and fetching the memory operand. The total number of clock periods, the number of read

cycles, and the number of write cycles (zero for all effective address calculations) are

shown in the previously described format.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 7-1

Table 7-1. Effective Address Calculation Times

Addressing Mode Byte Word Long

Register

Dn Data Register Direct 0(0/0) 0(0/0) 0(0/0)

An Address Register Direct 0(0/0) 0(0/0) 0(0/0)

Memory

(An) Address Register Indirect 4(1/0) 8(2/0) 16(4/0)

(An)+ Address Register Indirect with Postincrement 4(1/0) 8(2/0) 16(4/0)

–(An) Address Register Indirect with Predecrement 6(1/0) 10(2/0) 18(4/0)

(d 16, An) Address Register Indirect with Displacement 12(3/0) 16(4/0) 24(6/0)

(d 8, An, Xn)* Address Register Indirect with Index 14(3/0) 18(4/0) 26(6/0)

(xxx).W Absolute Short 12(3/0) 16(4/0) 24(6/0)

(xxx).L Absolute Long 20(5/0) 24(6/0) 32(8/0)

(d 16, PC) Program Counter Indirect with Displacement 12(3/0) 16(3/0) 24(6/0)

(d 8, PC, Xn)* Program Counter Indirect with Index 14(3/0) 18(4/0) 26(6/0)

#<data> Immediate 8(2/0) 8(2/0) 16(4/0)

*The size of the index register (Xn) does not affect execution time.

7.2 MOVE INSTRUCTION EXECUTION TIMES

Tables 7-2, 7-3, and 7-4 list the numbers of clock periods for the move instructions. The

totals include instruction fetch, operand reads, and operand writes. The total number of

clock periods, the number of read cycles, and the number of write cycles are shown in the

previously described format.

Table 7-2. Move Byte Instruction Execution Times

Destination

Source Dn An (An) (An)+ –(An) (d16, An) (d8, An, Xn)* (xxx).W (xxx).L

28(6/1)

20(4/1)

22(4/1)

20(4/1)

12(2/1)

12(2/1)

12(2/1)

8(2/0)

8(2/0)

Dn 28(6/1)

20(4/1)

22(4/1)

20(4/1)

12(2/1)

12(2/1)

12(2/1)

8(2/0)

8(2/0)

An 32(7/1)

24(5/1)

26(5/1)

24(5/1)

16(3/1)

16(3/1)

16(3/1)

12(3/0)

12(3/0)

(An) 32(7/1)

24(5/1)

26(5/1)

24(5/1)

16(3/1)

16(3/1)

16(3/1)

12(3/0)

12(3/0)

(An)+ 34(7/1)

26(5/1)

28(5/1)

26(5/1)

18(3/1)

18(3/1)

18(3/1)

14(3/0)

14(3/0)

–(An) 40(9/1)

32(7/1)

34(7/1)

32(7/1)

24(5/1)

24(5/1)

24(5/1)

20(5/0)

20(5/0)

(d 16, An) 42(9/1)

34(7/1)

36(7/1)

34(7/1)

26(5/1)

26(5/1)

26(5/1)

22(5/0)

22(5/0)

(d 8, An, Xn)* 40(9/1)

32(7/1)

34(7/1)

32(7/1)

24(5/1)

24(5/1)

24(5/1)

20(5/0)

20(5/0)

(xxx).W 48(11/1)

40(9/1)

42(9/1)

40(9/1)

32(7/1)

32(7/1)

32(7/1)

28(7/0)

28(7/0)

(xxx).L 40(9/1)

32(7/1)

34(7/1)

32(7/1)

24(5/1)

24(5/1)

24(5/1)

20(5/0)

20(5/0)

(d 16, PC) 42(9/1)

34(7/1)

36(7/1)

34(7/1)

26(5/1)

26(5/1)

26(5/1)

22(5/0)

22(5/0)

(d 8, PC, Xn)* 36(8/1)

28(6/1)

30(6/1)

28(6/1)

20(4/1)

20(4/1)

20(4/1)

16(4/0)

16(4/0)

#<data>

*The size of the index register (Xn) does not affect execution time.

7-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 7-3. Move Word Instruction Execution Times

Destination

Source Dn An (An) (An)+ –(An) (d16, An) (d8, An, Xn)* (xxx).W (xxx).L

32(6/2)

24(4/2)

26(4/2)

24(4/2)

16(2/2)

16(2/2)

16(2/2)

8(2/0)

8(2/0)

Dn 32(6/2)

24(4/2)

26(4/2)

24(4/2)

16(2/2)

16(2/2)

16(2/2)

8(2/0)

8(2/0)

An 40(8/2)

32(6/2)

34(6/2)

32(6/2)

24(4/2)

24(4/2)

24(4/2)

16(4/0)

16(4/0)

(An) 40(8/2)

32(6/2)

34(6/2)

32(6/2)

24(4/2)

24(4/2)

24(4/2)

16(4/0)

16(4/0)

(An)+ 42(8/2)

34(6/2)

32(6/2)

34(6/2)

26(4/2)

26(4/2)

26(4/2)

18(4/0)

18(4/0)

–(An) 48(10/2)

40(8/2)

42(8/2)

40(8/2)

32(6/2)

32(6/2)

32(6/2)

24(6/0)

24(6/0)

(d 16, An) 50(10/2)

42(8/2)

44(8/2)

42(8/2)

34(6/2)

34(6/2)

34(6/2)

26(6/0)

26(6/0)

(d 8, An, Xn)* 48(10/2)

40(8/2)

42(8/2)

40(8/2)

32(6/2)

32(6/2)

32(6/2)

24(6/0)

24(6/0)

(xxx).W 56(12/2)

48(10/2)

50(10/2)

48(10/2)

40(8/2)

40(8/2)

40(8/2)

32(8/0)

32(8/0)

(xxx).L 48(10/2)

40(8/2)

42(8/2)

40(8/2)

32(6/2)

32(6/2)

32(6/2)

24(6/0)

24(6/0)

(d 16, PC) 50(10/2)

42(8/2)

44(8/2)

42(8/2)

34(6/2)

34(6/2)

34(6/2)

26(6/0)

26(6/0)

(d 8, PC, Xn)* 40(8/2)

32(6/2)

34(6/2)

32(6/2)

24(4/2)

24(4/2)

24(4/2)

16(4/0)

16(4/0)

#<data>

*The size of the index register (Xn) does not affect execution time.

Table 7-4. Move Long Instruction Execution Times

Destination

Source Dn An (An) (An)+ –(An) (d16, An) (d8, An, Xn)* (xxx).W (xxx).L

40(6/4)

32(4/4)

34(4/4)

32(4/4)

24(2/4)

24(2/4)

24(2/4)

8(2/0)

8(2/0)

Dn 40(6/4)

32(4/4)

34(4/4)

32(4/4)

24(2/4)

24(2/4)

24(2/4)

8(2/0)

8(2/0)

An 56(10/4)

48(8/4)

50(8/4)

48(8/4)

40(6/4)

40(6/4)

40(6/4)

24(6/0)

24(6/0)

(An) 56(10/4)

48(8/4)

50(8/4)

48(8/4)

40(6/4)

40(6/4)

40(6/4)

24(6/0)

24(6/0)

(An)+ 58(10/4)

50(8/4)

52(8/4)

50(8/4)

42(6/4)

42(6/4)

42(6/4)

26(6/0)

26(6/0)

–(An) 64(12/4)

56(10/4)

58(10/4)

56(10/4)

48(8/4)

48(8/4)

48(8/4)

32(8/0)

32(8/0)

(d 16, An) 66(12/4)

58(10/4)

60(10/4)

58(10/4)

50(8/4)

50(8/4)

50(8/4)

34(8/0)

34(8/0)

(d 8, An, Xn)* 64(12/4)

56(10/4)

58(10/4)

56(10/4)

48(8/4)

48(8/4)

48(8/4)

32(8/0)

32(8/0)

(xxx).W 72(14/4)

64(12/4)

66(12/4)

64(12/4)

56(10/4)

56(10/4)

56(10/4)

40(10/0)

40(10/0)

(xxx).L 64(12/4)

56(10/4)

58(10/4)

56(10/4)

48(8/4)

48(8/4)

48(8/4)

32(8/0)

32(8/0)

(d 16, PC) 66(12/4)

58(10/4)

60(10/4)

58(10/4)

50(8/4)

50(8/4)

50(8/4)

34(8/0)

34(8/0)

(d 8, PC, Xn)* 56(10/4)

48(8/4)

50(8/4)

48(8/4)

40(6/4)

40(6/4)

40(6/4)

24(6/0)

24(6/0)

#<data>

*The size of the index register (Xn) does not affect execution time.

7.3 STANDARD INSTRUCTION EXECUTION TIMES

The numbers of clock periods shown in Table 7-5 indicate the times required to perform

the operations, store the results, and read the next instruction. The total number of clock

periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 7-3

In Table 7-5, the following notation applies:

An — Address register operand

Dn — Data register operand

ea — An operand specified by an effective address

M — Memory effective address operand

Table 7-5. Standard Instruction Execution Times

Instruction Size op<ea>, An op<ea>, Dn op Dn, <M>

12(2/1)+

8(2/0)+

—

ADD/ADDA Byte 16(2/2)+

8(2/0)+

12(2/0)+

Word 24(2/4)+

10(2/0)+**

10(2/0)+**

Long 12(2/1)+

8(2/0)+

—

AND Byte 16(2/2)+

8(2/0)+

—

Word 24(2/4)+

10(2/0)+**

—

Long —

8(2/0)+

—

CMP/CMPA Byte —

8(2/0)+

10(2/0)+

Word —

10(2/0)+

10(2/0)+

Long

DIVS — — 162(2/0)+* —

DIVU — — 144(2/0)+* —

12(2/1)+

8(2/0)+***

—

EOR Byte, 16(2/2)+

8(2/0)+***

—

Word, 24(2/4)+

12(2/0)+***

—

Long

MULS — — 74(2/0)+* —

MULU — — 74(2/0)+* —

12(2/1)+

8(2/0)+

—

OR Byte, 16(2/2)+

8(2/0)+

—

Word 24(2/4)+

10(2/0)+**

—

Long 12(2/1)+

8(2/0)+

SUB Byte, 16(2/2)+

8(2/0)+

Word 12(2/0)+ 24(2/4)+

10(2/0)+**

Long 10(2/0)+**

+ Add effective address calculation time.

* Indicates maximum base value added to word effective address time

** The base time of 10 clock periods is increased to 12 if the effective address mode is

register direct or immediate (effective address time should also be added).

*** Only available effective address mode is data register direct.

DIVS, DIVU — The divide algorithm used by the MC68008 provides less than 10% difference

between the best- and worst-case timings.

MULS, MULU — The multiply algorithm requires 42+2n clocks where n is defined as:

MULS: n = tag the <ea> with a zero as the MSB; n is the resultant number of 10

or 01 patterns in the 17-bit source; i.e., worst case happens when the source

is $5555.

MULU: n = the number of ones in the <ea>

7.4 IMMEDIATE INSTRUCTION EXECUTION TIMES

The numbers of clock periods shown in Table 7-6 include the times to fetch immediate

operands, perform the operations, store the results, and read the next operation. The total

number of clock periods, the number of read cycles, and the number of write cycles are

7-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

shown in the previously described format. The number of clock periods, the number of

read cycles, and the number of write cycles, respectively, must be added to those of the

effective address calculation where indicated by a plus sign (+).

In Table 7-6, the following notation applies:

# — Immediate operand

Dn — Data register operand

An — Address register operand

M — Memory operand

Table 7-6. Immediate Instruction Execution Times

Instruction Size op #, Dn op #, An op #, M

— 20(4/1)+

16(4/0)

ADDI Byte — 24(4/2)+

16(4/0)

Word 40(6/4)+

28(6/0)

Long — 12(2/1)+

—

8(2/0)

ADDQ Byte 16(2/2)+

12(2/0)

8(2/0)

Word 24(2/4)+

12(2/0)

12(2/0)

Long 20(4/1)+

—

16(4/0)

ANDI Byte 24(4/2)+

—

16(4/0)

Word 40(6/4)+

—

28(6/0)

Long 16(4/0)

—

16(4/0)

CMPI Byte 16(4/0)

—

16(4/0)

Word 24(6/0)

—

26(6/0)

Long 20(4/1)+

—

16(4/0)

EORI Byte 24(4/2)+

—

16(4/0)

Word 40(6/4)+

—

28(6/0)

Long

MOVEQ Long 8(2/0) — —

20(4/1)+

—

16(4/0)

ORI Byte 24(4/2)+

—

16(4/0)

Word 40(6/4)+

—

28(6/0)

Long 12(2/1)+

—

16(4/0)

SUBI Byte 16(2/2)+

—

16(4/0)

Word 24(2/4)+

—

28(6/0)

Long 20(4/1)+

—

8(2/0)

SUBQ Byte 24(4/2)+

12(2/0)

8(2/0)

Word 40(6/4)+

12(2/0)

12(2/0)

Long

+Add effective address calculation time.

7.5 SINGLE OPERAND INSTRUCTION EXECUTION TIMES

Table 7-7 lists the timing data for the single operand instructions. The total number of

clock periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 7-5

Table 7-7. Single Operand Instruction

Execution Times

Instruction Size Register Memory

CLR Byte 8(2/0) 12(2/1)+

Word 8(2/0) 16(2/2)+

Long 10(2/0) 24(2/4)+

NBCD Byte 10(2/0) 12(2/1)+

NEG Byte 8(2/0) 12(2/1)+

Word 8(2/0) 16(2/2)+

Long 10(2/0) 24(2/4)+

NEGX Byte 8(2/0) 12(2/1)+

Word 8(2/0) 16(2/2)+

Long 10(2/0) 24(2/4)+

NOT Byte 8(2/0) 12(2/1)+

Word 8(2/0) 16(2/2)+

Long 10(2/0) 24(2/4)+

Scc Byte, False 8(2/0) 12(2/1)+

Byte, True 10(2/0) 12(2/1)+

TAS Byte 8(2/0) 14(2/1)+

TST Byte 8(2/0) 8(2/0)+

Word 8(2/0) 8(2/0)+

Long 8(2/0) 8(2/0)+

+Add effective address calculation time.

7.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES

Table 7-8 lists the timing data for the shift and rotate instructions. The total number of

clock periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

Table 7-8. Shift/Rotate Instruction Execution Times

Instruction Size Register Memory

ASR, ASL Byte 10+2n (2/0) —

Word 10+2n (2/0) 16(2/2)+

Long 12+n2 (2/0) —

LSR, LSL Byte 10+2n (2/0) —

Word 10+2n (2/0) 16(2/2)+

Long 12+n2 (2/0) —

ROR, ROL Byte 10+2n (2/0) —

Word 10+2n (2/0) 16(2/2)+

Long 12+n2 (2/0) —

ROXR, ROXL Byte 10+2n (2/0) —

Word 10+2n (2/0) 16(2/2)+

Long 12+n2 (2/0) —

+Add effective address calculation time for word operands.

n is the shift count.

7-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

7.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES

Table 7-9 lists the timing data for the bit manipulation instructions. The total number of

clock periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

Table 7-9. Bit Manipulation Instruction Execution Times

Dynamic Static

Instruction Size Register Memory Register Memory

BCHG Byte — 12(2/1)+ — 20(4/1)+

Long 12(2/0)* — 20(4/0)* —

BCLR Byte — 12(2/1)+ — 20(4/1)+

Long 14(2/0)* — 22(4/0)* —

BSET Byte — 12(2/1)+ — 20(4/1)+

Long 12(2/0)* — 20(4/0)* —

BTST Byte — 8(2/0)+ — 16(4/0)+

Long 10(2/0) 18(4/0) —

+Add effective address calculation time.

* Indicates maximum value; data addressing mode only.

7.8 CONDITIONAL INSTRUCTION EXECUTION TIMES

Table 7-10 lists the timing data for the conditional instructions. The total number of clock

periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

Table 7-10. Conditional Instruction Execution Times

Trap or Branch Trap or Branch

Instruction Displacement Taken Not Taken

Bcc Byte 18(4/0) 12(2/0)

Word 18(4/0) 20(4/0)

BRA Byte 18(4/0) —

Word 18(4/0) —

BSR Byte 34(4/4) —

Word 34(4/4) —

DBcc CC True — 20(4/0)

CC False 18(4/0) 26(6/0)

CHK — 68(8/6)+* 14(2/0)

TRAP — 62(8/6) —

TRAPV — 66(10/6) 8(2/0)

+Add effective address calculation time for word operand.

* Indicates maximum base value.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 7-7

7.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION

EXECUTION TIMES

Table 7-11 lists the timing data for the jump (JMP), jump to subroutine (JSR), load

effective address (LEA), push effective address (PEA), and move multiple registers

(MOVEM) instructions. The total number of clock periods, the number of read cycles, and

the number of write cycles are shown in the previously described format.

Table 7-11. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times

Instruction Size (An) (An)+ –(An) (d ,An) (d 8,An,Xn)+ (xxx).W (xxx).L (d PC) (d 8, PC, Xn)*

16 16

JMP — 16 (4/0) — — 18 (4/0) 22 (4/0) 18 (4/0) 24 (6/0) 18 (4/0) 22 (4/0)

JSR — 32 (4/4) — — 34 (4/4) 38 (4/4) 34 (4/4) 40 (6/4) 34 (4/4) 32 (4/4)

LEA — 8(2/0) — — 16 (4/0) 20 (4/0) 16 (4/0) 24 (6/0) 16 (4/0) 20 (4/0)

PEA — 24 (2/4) — — 32 (4/4) 36 (4/4) 32 (4/4) 40 (6/4) 32 (4/4) 36 (4/4)

MOVEM Word 24+8n 24+8n — 32+8n 34+8n 32+8n 40+8n 32+8n 34+8n

→

M R (6+2n/0) (6+2n/0) (8+2n/0) (8+2n/0) (10+n/0) (10+2n/0) (8+2n/0) (8+2n/0)

Long 24+16n 24+16n — 32+16n 34+16n 32+16n 40+16n 32+16n 34+16n

(6+4n/0) (6+4n/0) (8+4n/0) (8+4n/0) (8+4n/0) (8+4n/0) (8+4n/0) (8+4n/0)

MOVEM Word 16+8n — 16+8n 24+8n 26+8n 24+8n 32+8n — —

→

R M (4/2n) — (4/2n) (6/2n) (6/2n) (6/2n) (8/2n) — —

Long 16+16n — 16+16n 24+16n 26+16n 24+16n 32+16n — —

(4/4n) — (4/4n) (6/4n) (8/4n) (6/4n) — —

n is the number of registers to move.

*The size of the index register (Xn) does not affect the instruction's execution time.

7.10 MULTIPRECISION INSTRUCTION EXECUTION TIMES

Table 7-12 lists the timing data for multiprecision instructions. The numbers of clock

periods include the times to fetch both operands, perform the operations, store the results,

and read the next instructions. The total number of clock periods, the number of read

cycles, and the number of write cycles are shown in the previously described format.

The following notation applies in Table 7-12:

Dn — Data register operand

M — Memory operand

7-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 7-12. Multiprecision Instruction

Execution Times

Instruction Size op Dn, Dn op M, M

22(4/1)

8(2/0)

ADDX Byte 50(6/2)

8(2/0)

Word 58(10/4)

12(2/0)

Long 16(4/0)

—

CMPM Byte, 24(6/0)

—

Word 40(10/0)

—

Long 22(4/1)

8(2/0)

SUBX Byte, \ 50(6/2)

8(2/0)

Word 58(10/4)

12(2/0)

Long

ABCD Byte 10(2/0) 20(4/1)

SBCD Byte 10(2/0) 20(4/1)

7.11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES

Tables 7-13 and 7-14 list the timing data for miscellaneous instructions. The total number

of clock periods, the number of read cycles, and the number of write cycles are shown in

the previously described format. The number of clock periods, the number of read cycles,

and the number of write cycles, respectively, must be added to those of the effective

address calculation where indicated by a plus sign (+).

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 7-9

Table 7-13. Miscellaneous Instruction Execution Times

Instruction Register Memory

ANDI to CCR 32(6/0) —

ANDI to SR 32(6/0) —

EORI to CCR 32(6/0) —

EORI to SR 32(6/0) —

EXG 10(2/0) —

EXT 8(2/0) —

LINK 32(4/4) —

MOVE to CCR 18(4/0) 18(4/0)+

MOVE to SR 18(4/0) 18(4/0)+

MOVE from SR 10(2/0) 16(2/2)+

MOVE to USP 8(2/0) —

MOVE from USP 8(2/0) —

NOP 8(2/0) —

ORI to CCR 32(6/0) —

ORI to SR 32(6/0) —

RESET 136(2/0) —

RTE 40(10/0) —

RTR 40(10/0) —

RTS 32(8/0) —

STOP 4(0/0) —

SWAP 8(2/0) —

TRAPV (No Trap) 8(2/0) —

UNLK 24(6/0) —

+Add effective address calculation time for word operand.

Table 7-14. Move Peripheral Instruction Execution Times

→ →

Instruction Size Register Memory Memory Register

MOVEP Word 24(4/2) 24(6/0)

Long 32(4/4) 32(8/0)

+Add effective address calculation time.

7.12 EXCEPTION PROCESSING EXECUTION TIMES

Table 7-15 lists the timing data for exception processing. The numbers of clock periods

include the times for all stacking, the vector fetch, and the fetch of the first instruction of

the handler routine. The total number of clock periods, the number of read cycles, and the

number of write cycles are shown in the previously described format. The number of clock

7-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

periods, the number of read cycles, and the number of write cycles, respectively, must be

added to those of the effective address calculation where indicated by a plus sign (+).

Table 7-15. Exception Processing

Execution Times

Exception Periods

Address Error 94(8/14)

Bus Error 94(8/14)

CHK Instruction 68(8/6)+

Divide by Zero 66(8/6)+

Interrupt 72(9/6)*

Illegal Instruction 62(8/6)

Privilege Violation 62(8/6)

** 64(12/0)

RESET

Trace 62(8/6)

TRAP Instruction 62(8/6)

TRAPV Instruction 66(10/6)

+ Add effective address calculation time.

** Indicates the time from when and are first

RESET HALT

sampled as negated to when instruction execution starts.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 7-11

SECTION 8

16-BIT INSTRUCTION

EXECUTION TIMES

This section contains listings of the instruction execution times in terms of external clock

(CLK) periods for the MC68000, MC68HC000, MC68HC001, and the MC68EC000 in 16-

bit mode. In this data, it is assumed that both memory read and write cycles consist of four

clock periods. A longer memory cycle causes the generation of wait states that must be

added to the total instruction times.

The number of bus read and write cycles for each instruction is also included with the

timing data. This data is shown as n(r/w)

where:

n is the total number of clock periods

r is the number of read cycles

w is the number of write cycles

For example, a timing number shown as 18(3/1) means that the total number of clock

periods is 18. Of the 18 clock periods, 12 are used for the three read cycles (four periods

per cycle). Four additional clock periods are used for the single write cycle, for a total of 16

clock periods. The bus is idle for two clock periods during which the processor completes

the internal operations required for the instruction.

NOTE

The total number of clock periods (n) includes instruction fetch

and all applicable operand fetches and stores.

8.1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES

Table 8-1 lists the numbers of clock periods required to compute the effective addresses

for instructions. The total includes fetching any extension words, computing the address,

and fetching the memory operand. The total number of clock periods, the number of read

cycles, and the number of write cycles (zero for all effective address calculations) are

shown in the previously described format.

MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL 8-1

Table 8-1. Effective Address Calculation Times

Addressing Mode Byte, Word Long

Register

Dn Data Register Direct 0(0/0) 0(0/0)

An Address Register Direct 0(0/0) 0(0/0)

Memory

(An) Address Register Indirect 4(1/0) 8(2/0)

(An)+ Address Register Indirect with Postincrement 4(1/0) 8(2/0)

–(An) Address Register Indirect with Predecrement 6(1/0) 10(2/0)

(d 16, An) Address Register Indirect with Displacement 8(2/0) 12(3/0)

(d 8, An, Xn)* Address Register Indirect with Index 10(2/0) 14(3/0)

(xxx).W Absolute Short 8(2/0) 12(3/0)

(xxx).L Absolute Long 12(3/0) 16(4/0)

(d 8, PC) Program Counter Indirect with Displacement 8(2/0) 12(3/0)

(d 16, PC, Xn)* Program Counter Indirect with Index 10(2/0) 14(3/0)

#<data> Immediate 4(1/0) 8(2/0)

*The size of the index register (Xn) does not affect execution time.

8.2 MOVE INSTRUCTION EXECUTION TIMES

Tables 8-2 and 8-3 list the numbers of clock periods for the move instructions. The totals

include instruction fetch, operand reads, and operand writes. The total number of clock

periods, the number of read cycles, and the number of write cycles are shown in the

previously described format.

Table 8-2. Move Byte and Word Instruction Execution Times

Destination

Source Dn An (An) (An)+ –(An) (d16, An) (d8, An, Xn)* (xxx).W (xxx).L

16(3/1)

12(2/1)

14(2/1)

12(2/1)

8(1/1)

8(1/1)

8(1/1)

4(1/0)

4(1/0)

Dn 16(3/1)

12(2/1)

14(2/1)

12(2/1)

8(1/1)

8(1/1)

8(1/1)

4(1/0)

4(1/0)

An 20(4/1)

16(3/1)

18(3/1)

16(3/1)

12(2/1)

12(2/1)

12(2/1)

8(2/0)

8(2/0)

(An) 20(4/1)

16(3/1)

18(3/1)

16(3/1)

12(2/1)

12(2/1)

12(2/1)

8(2/0)

8(2/0)

(An)+ 22(4/1)

18(3/1)

20(3/1)

18(3/1)

14(2/1)

14(2/1)

14(2/1)

10(2/0)

10(2/0)

–(An) 24(5/1)

20(4/1)

22(4/1)

20(4/1)

16(3/1)

16(3/1)

16(3/1)

12(3/0)

12(3/0)

(d 16, An) 26(5/1)

22(4/1)

24(4/1)

22(4/1)

18(3/1)

18(3/1)

18(3/1)

14(3/0)

14(3/0)

(d 8, An, Xn)* 24(5/1)

20(4/1)

22(4/1)

20(4/1)

16(3/1)

16(3/1)

16(3/1)

12(3/0)

12(3/0)

(xxx).W 28(6/1)

24(5/1)

26(5/1)

24(5/1)

20(4/1)

20(4/1)

20(4/1)

16(4/0)

16(4/0)

(xxx).L 24(5/1)

20(4/1)

22(4/1)

20(4/1)

16(3/1)

16(3/1)

16(3/1)

12(3/0)

12(3/0)

(d 16, PC) 26(5/1)

22(4/1)

24(4/1)

22(4/1)

18(3/1)

18(3/1)

18(3/1)

14(3/0)

14(3/0)

(d 8, PC, Xn)* 20(4/1)

16(3/1)

18(3/1)

16(3/1)

12(2/1)

12(2/1)

12(2/1)

8(2/0)

8(2/0)

#<data>

*The size of the index register (Xn) does not affect execution time.

8-2 MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL MOTOROLA

Table 8-3. Move Long Instruction Execution Times

Destination

Source Dn An (An) (An)+ –(An) (d16, An) (d8, An, Xn)* (xxx).W (xxx).L

20(3/2)

16(2/2)

18(2/2)

16(2/2)

12(1/2)

12(1/2)

12(1/2)

4(1/0)

4(1/0)

Dn 20(3/2)

16(2/2)

18(2/2)

16(2/2)

12(1/2)

12(1/2)

12(1/2)

4(1/0)

4(1/0)

An 28(5/2)

24(4/2)

26(4/2)

24(4/2)

20(3/2)

20(3/2)

20(3/2)

12(3/0)

12(3/0)

(An) 28(5/2)

24(4/2)

26(4/2)

24(4/2)

20(3/2)

20(3/2)

20(3/2)

12(3/0)

12(3/0)

(An)+ 30(5/2)

26(4/2)

28(4/2)

26(4/2)

22(3/2)

22(3/2)

22(3/2)

14(3/0)

14(3/0)

–(An) 32(6/2)

28(5/2)

30(5/2)

28(5/2)

24(4/2)

24(4/2)

24(4/2)

16(4/0)

16(4/0)

(d 16, An) 34(6/2)

30(5/2)

32(5/2)

30(5/2)

26(4/2)

26(4/2)

26(4/2)

18(4/0)

18(4/0)

(d 8, An, Xn)* 32(6/2)

28(5/2)

30(5/2)

28(5/2)

24(4/2)

24(4/2)

24(4/2)

16(4/0)

16(4/0)

(xxx).W 36(7/2)

32(6/2)

34(6/2)

32(6/2)

28(5/2)

28(5/2)

28(5/2)

20(5/0)

20(5/0)

(xxx).L 32(5/2)

28(5/2)

30(5/2)

28(5/2)

24(4/2)

24(4/2)

24(4/2)

16(4/0)

16(4/0)

(d, PC) 34(6/2)

30(5/2)

32(5/2)

30(5/2)

26(4/2)

26(4/2)

26(4/2)

18(4/0)

18(4/0)

(d, PC, Xn)* 28(5/2)

24(4/2)

26(4/2)

24(4/2)

20(3/2)

20(3/2)

20(3/2)

12(3/0)

12(3/0)

#<data>

*The size of the index register (Xn) does not affect execution time.

8.3 STANDARD INSTRUCTION EXECUTION TIMES

The numbers of clock periods shown in Table 8-4 indicate the times required to perform

the operations, store the results, and read the next instruction. The total number of clock

periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

In Table 8-4, the following notation applies:

An — Address register operand

Dn — Data register operand

ea — An operand specified by an effective address

M — Memory effective address operand

MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL 8-3

Table 8-4. Standard Instruction Execution Times

Instruction Size op<ea>, An† op<ea>, Dn op Dn, <M>

ADD/ADDA Byte, Word 8(1/0)+ 4(1/0)+ 8(1/1)+

Long 6(1/0)+** 6(1/0)+** 12(1/2)+

AND Byte, Word — 4(1/0)+ 8(1/1)+

Long — 6(1/0)+** 12(1/2)+

CMP/CMPA Byte, Word 6(1/0)+ 4(1/0)+ —

Long 6(1/0)+ 6(1/0)+ —

DIVS — — 158(1/0)+* —

DIVU — — 140(1/0)+* —

EOR Byte, Word — 4(1/0)*** 8(1/1)+

Long — 8(1/0)*** 12(1/2)+

MULS — — 70(1/0)+* —

MULU — — 70(1/0)+* —

OR Byte, Word — 4(1/0)+ 8(1/1)+

Long — 6(1/0)+** 12(1/2)+

SUB Byte, Word 8(1/0)+ 4(1/0)+ 8(1/1)+

Long 6(1/0)+** 6(1/0)+** 12(1/2)+

+ Add effective address calculation time.

† Word or long only

* Indicates maximum basic value added to word effective address time

** The base time of six clock periods is increased to eight if the effective address mode is

register direct or immediate (effective address time should also be added).

*** Only available effective address mode is data register direct.

DIVS, DIVU — The divide algorithm used by the MC68000 provides less than 10% difference

between the best- and worst-case timings.

MULS, MULU — The multiply algorithm requires 38+2n clocks where n is defined as:

MULU: n = the number of ones in the <ea>

MULS: n=concatenate the <ea> with a zero as the LSB; n is the resultant number of 10

or 01 patterns in the 17-bit source; i.e., worst case happens when the source

is $5555.

8.4 IMMEDIATE INSTRUCTION EXECUTION TIMES

The numbers of clock periods shown in Table 8-5 include the times to fetch immediate

operands, perform the operations, store the results, and read the next operation. The total

number of clock periods, the number of read cycles, and the number of write cycles are

shown in the previously described format. The number of clock periods, the number of

read cycles, and the number of write cycles, respectively, must be added to those of the

effective address calculation where indicated by a plus sign (+).

In Table 8-5, the following notation applies:

# — Immediate operand

Dn — Data register operand

An — Address register operand

M — Memory operand

8-4 MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL MOTOROLA

Table 8-5. Immediate Instruction Execution Times

Instruction Size op #, Dn op #, An op #, M

ADDI Byte, Word 8(2/0) — 12(2/1)+

Long 16(3/0) — 20(3/2)+

ADDQ Byte, Word 4(1/0) 4(1/0)* 8(1/1)+

Long 8(1/0) 8(1/0) 12(1/2)+

ANDI Byte, Word 8(2/0) — 12(2/1)+

Long 14(3/0) — 20(3/2)+

CMPI Byte, Word 8(2/0) — 8(2/0)+

Long 14(3/0) — 12(3/0)+

EORI Byte, Word 8(2/0) — 12(2/1)+

Long 16(3/0) — 20(3/2)+

MOVEQ Long 4(1/0) — —

ORI Byte, Word 8(2/0) — 12(2/1)+

Long 16(3/0) — 20(3/2)+

SUBI Byte, Word 8(2/0) — 12(2/1)+

Long 16(3/0) — 20(3/2)+

SUBQ Byte, Word 4(1/0) 8(1/0)* 8(1/1)+

Long 8(1/0) 8(1/0) 12(1/2)+

8.5 SINGLE OPERAND INSTRUCTION EXECUTION TIMES

Table 8-6 lists the timing data for the single operand instructions. The total number of

clock periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL 8-5

Table 8-6. Single Operand Instruction

Execution Times

Instruction Size Register Memory

CLR Byte, Word 4(1/0) 8(1/1)+

Long 6(1/0) 12(1/2)+

NBCD Byte 6(1/0) 8(1/1)+

NEG Byte, Word 4(1/0) 8(1/1)+

Long 6(1/0) 12(1/2)+

NEGX Byte, Word 4(1/0) 8(1/1)+

Long 6(1/0) 12(1/2)+

NOT Byte, Word 4(1/0) 8(1/1)+

Long 6(1/0) 12(1/2)+

Scc Byte, False 4(1/0) 8(1/1)+

Byte, True 6(1/0) 8(1/1)+

TAS Byte 4(1/0) 14(2/1)+

TST Byte, Word 4(1/0) 4(1/0)+

Long 4(1/0) 4(1/0)+

+Add effective address calculation time.

8.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES

Table 8-7 lists the timing data for the shift and rotate instructions. The total number of

clock periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

Table 8-7. Shift/Rotate Instruction Execution Times

Instruction Size Register Memory

ASR, ASL Byte, Word 6+2n (1/0) 8(1/1)+

Long 8+2n (1/0) —

LSR, LSL Byte, Word 6+2n (1/0) 8(1/1)+

Long 8+2n (1/0) —

ROR, ROL Byte, Word 6+2n (1/0) 8(1/1)+

Long 8+2n (1/0) —

ROXR, ROXL Byte, Word 6+2n (1/0) 8(1/1)+

Long 8+2n (1/0) —

+Add effective address calculation time for word operands.

n is the shift count.

8-6 MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL MOTOROLA

8.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES

Table 8-8 lists the timing data for the bit manipulation instructions. The total number of

clock periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

Table 8-8. Bit Manipulation Instruction Execution Times

Dynamic Static

Instruction Size Register Memory Register Memory

BCHG Byte — 8(1/1)+ — 12(2/1)+

Long 8(1/0)* — 12(2/0)* —

BCLR Byte — 8(1/1)+ — 12(2/1)+

Long 10(1/0)* — 14(2/0)* —

BSET Byte — 8(1/1)+ — 12(2/1)+

Long 8(1/0)* — 12(2/0)* —

BTST Byte — 4(1/0)+ — 8(2/0)+

Long 6(1/0) — 10(2/0) —

+Add effective address calculation time.

* Indicates maximum value; data addressing mode only.

8.8 CONDITIONAL INSTRUCTION EXECUTION TIMES

Table 8-9 lists the timing data for the conditional instructions. The total number of clock

periods, the number of read cycles, and the number of write cycles are shown in the

previously described format.

Table 8-9. Conditional Instruction Execution Times

Branch Branch Not

Instruction Displacement Taken Taken

Bcc Byte 10(2/0) 8(1/0)

Word 10(2/0) 12(2/0)

BRA Byte 10(2/0) —

Word 10(2/0) —

BSR Byte 18(2/2) —

Word 18(2/2) —

DBcc cc true — 12(2/0)

cc false, Count Not Expired 10(2/0) —

cc false, Counter Expired — 14(3/0)

MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL 8-7

8.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION

EXECUTION TIMES

Table 8-10 lists the timing data for the jump (JMP), jump to subroutine (JSR), load

effective address (LEA), push effective address (PEA), and move multiple registers

(MOVEM) instructions. The total number of clock periods, the number of read cycles, and

the number of write cycles are shown in the previously described format.

Table 8-10. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times

Instruction Size (An) (An)+ –(An) (d ,An) (d 8,An,Xn)+ (xxx).W (xxx).L (d PC) (d 8, PC, Xn)*

16 16

JMP — 8(2/0) — — 10 (2/0) 14 (3/0) 10 (2/0) 12 (3/0) 10 (2/0) 14 (3/0)

JSR — 16 (2/2) — — 18 (2/2) 22 (2/2) 18 (2/2) 20 (3/2) 18 (2/2) 22 (2/2)

LEA — 4(1/0) — — 8(2/0) 12 (2/0) 8(2/0) 12 (3/0) 8(2/0) 12 (2/0)

PEA — 12 (1/2) — — 16 (2/2) 20 (2/2) 16 (2/2) 20 (3/2) 16 (2/2) 20 (2/2)

MOVEM Word 12+4n 12+4n — 16+4n 18+4n 16+4n 20+4n 16+4n 18+4n (4+n/0)

→

M R (3+n/0) (3+n/0) (4+n/0) (4+n/0) (4+n/0) (5+n/0) (4n/0)

Long 12+8n 12+8n — 16+8n 18+8n 16+8n 20+8n 16+8n 18+8n

(3+2n/0) (3+n/0) (4+2n/0) (4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)

MOVEM Word 8+4n — 8+4n 12+4n 14+4n 12+4n 16+4n — —

→

R M (2/n) (2/n) (3/n) (3/n) (3/n) (4/n) — —

Long 8+8n — 8+8n 12+8n 14+8n 12+8n 16+8n — —

(2/2n) — (2/2n) (3/2n) (3/2n) (3/2n) (4/2n) — —

n is the number of registers to move.

*The size of the index register (Xn) does not affect the instruction's execution time.

8.10 MULTIPRECISION INSTRUCTION EXECUTION TIMES

Table 8-11 lists the timing data for multiprecision instructions. The number of clock periods

includes the time to fetch both operands, perform the operations, store the results, and

read the next instructions. The total number of clock periods, the number of read cycles,

and the number of write cycles are shown in the previously described format.

The following notation applies in Table 8-11:

Dn — Data register operand

M — Memory operand

8-8 MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL MOTOROLA

Table 8-11. Multiprecision Instruction

Execution Times

Instruction Size op Dn, Dn op M, M

ADDX Byte, Word 4(1/0) 18(3/1)

Long 8(1/0) 30(5/2)

CMPM Byte, Word — 12(3/0)

Long — 20(5/0)

SUBX Byte, Word 4(1/0) 18(3/1)

Long 8(1/0) 30(5/2)

ABCD Byte 6(1/0) 18(3/1)

SBCD Byte 6(1/0) 18(3/1)

8.11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES

Tables 8-12 and 8-13 list the timing data for miscellaneous instructions. The total number

of clock periods, the number of read cycles, and the number of write cycles are shown in

the previously described format. The number of clock periods, the number of read cycles,

and the number of write cycles, respectively, must be added to those of the effective

address calculation where indicated by a plus sign (+).

MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL 8-9

Table 8-12. Miscellaneous Instruction Execution Times

Instruction Size Register Memory

ANDI to CCR Byte 20(3/0) —

ANDI to SR Word 20(3/0) —

CHK (No Trap) — 10(1/0)+ —

EORI to CCR Byte 20(3/0) —

EORI to SR Word 20(3/0) —

ORI to CCR Byte 20(3/0) —

ORI to SR Word 20(3/0) —

MOVE from SR — 6(1/0) 8(1/1)+

MOVE to CCR — 12(1/0) 12(1/0)+

MOVE to SR — 12(2/0) 12(2/0)+

EXG — 6(1/0) —

EXT Word 4(1/0) —

Long 4(1/0) —

LINK — 16(2/2) —

MOVE from USP — 4(1/0) —

MOVE to USP — 4(1/0) —

NOP — 4(1/0) —

RESET — 132(1/0) —

RTE — 20(5/0) —

RTR — 20(2/0) —

RTS — 16(4/0) —

STOP — 4(0/0) —

SWAP — 4(1/0) —

TRAPV — 4(1/0) —

UNLK — 12(3/0) —

+Add effective address calculation time.

Table 8-13. Move Peripheral Instruction Execution Times

→ →

Instruction Size Register Memory Memory Register

MOVEP Word 16(2/2) 16(4/0)

Long 24(2/4) 24(6/0)

8.12 EXCEPTION PROCESSING EXECUTION TIMES

Table 8-14 lists the timing data for exception processing. The numbers of clock periods

include the times for all stacking, the vector fetch, and the fetch of the first instruction of

8-10 MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL MOTOROLA

the handler routine. The total number of clock periods, the number of read cycles, and the

number of write cycles are shown in the previously described format. The number of clock

periods, the number of read cycles, and the number of write cycles, respectively, must be

added to those of the effective address calculation where indicated by a plus sign (+).

Table 8-14. Exception Processing

Execution Times

Exception Periods

Address Error 50(4/7)

Bus Error 50(4/7)

CHK Instruction 40(4/3)+

Divide by Zero 38(4/3)+

Illegal Instruction 34(4/3)

Interrupt 44(5/3)*

Privilege Violation 34(4/3)

** 40(6/0)

RESET

Trace 34(4/3)

TRAP Instruction 34(4/3)

TRAPV Instruction 34(5/3)

+ Add effective address calculation time.

* The interrupt acknowledge cycle is assumed to take

four clock periods.

** Indicates the time from when and are first

RESET HALT

sampled as negated to when instruction execution starts.

MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL 8-11

SECTION 9

MC68010 INSTRUCTION EXECUTION TIMES

This section contains listings of the instruction execution times in terms of external clock

(CLK) periods for the MC68010. In this data, it is assumed that both memory read and

write cycles consist of four clock periods. A longer memory cycle causes the generation of

wait states that must be added to the total instruction times.

The number of bus read and write cycles for each instruction is also included with the

timing data. This data is shown as n(r/w)

where:

n is the total number of clock periods

r is the number of read cycles

w is the number of write cycles

For example, a timing number shown as 18(3/1) means that 18 clock cycles are required

to execute the instruction. Of the 18 clock periods, 12 are used for the three read cycles

(four periods per cycle). Four additional clock periods are used for the single write cycle,

for a total of 16 clock periods. The bus is idle for two clock periods during which the

processor completes the internal operations required for the instructions.

NOTE

The total number of clock periods (n) includes instruction fetch

and all applicable operand fetches and stores.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 9-1

9.1 OPERAND EFFECTIVE ADDRESS CALCULATION TIMES

Table 9-1 lists the numbers of clock periods required to compute the effective addresses

for instructions. The totals include fetching any extension words, computing the address,

and fetching the memory operand. The total number of clock periods, the number of read

cycles, and the number of write cycles (zero for all effective address calculations) are

shown in the previously described format.

Table 9-1. Effective Address Calculation Times

Byte, Word Long

Addressing Mode Fetch No Fetch Fetch No Fetch

Register

Dn Data Register Direct 0(0/0) — 0(0/0) —

An Address Register Direct 0(0/0) — 0(0/0) —

Memory

(An) Address Register Indirect 4(1/0) 2(0/0) 8(2/0) 2(0/0)

(An)+ Address Register Indirect with Postincrement 4(1/0) 4(0/0) 8(2/0) 4(0/0)

–(An) Address Register Indirect with Predecrement 6(1/0) 4(0/0) 10(2/0) 4(0/0)

(d 16, An) Address Register Indirect with Displacement 8(2/0) 4(0/0) 12(3/0) 4(1/0)

(d 8, An, Xn)* Address Register Indirect with Index 10(2/0) 8(1/0) 14(3/0) 8(1/0)

(xxx).W Absolute Short 8(2/0) 4(1/0) 12(3/0) 4(1/0)

(xxx).L Absolute Long 12(3/0) 8(2/0) 16(4/0) 8(2/0)

(d 16, PC) Program Counter Indirect with Displacement 8(2/0) — 12(3/0) —

(d 8, PC, Xn)* Program Counter Indirect with Index 10(2/0) — 14(3/0) —

#<data> Immediate 4(1/0) — 8(2/0) —

*The size of the index register (Xn) does not affect execution time.

9.2 MOVE INSTRUCTION EXECUTION TIMES

Tables 9-2, 9-3, 9-4, and 9-5 list the numbers of clock periods for the move instructions.

The totals include instruction fetch, operand reads, and operand writes. The total number

of clock periods, the number of read cycles, and the number of write cycles are shown in

the previously described format.

9-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 9-2. Move Byte and Word Instruction Execution Times

Destination

Source Dn An (An) (An)+ –(An) (d16, An) (d8, An, Xn)* (xxx).W (xxx).L

16(3/1)

12(2/1)

14(2/1)

12(2/1)

8(1/1)

8(1/1)

8(1/1)

4(1/0)

4(1/0)

Dn 16(3/1)

12(2/1)

14(2/1)

12(2/1)

8(1/1)

8(1/1)

8(1/1)

4(1/0)

4(1/0)

An 20(4/1)

16(3/1)

18(3/1)

16(3/1)

12(2/1)

12(2/1)

12(2/1)

8(2/0)

8(2/0)

(An) 20(4/1)

16(3/1)

18(3/1)

16(3/1)

12(2/1)

12(2/1)

12(2/1)

8(2/0)

8(2/0)

(An)+ 22(4/1)

18(3/1)

20(3/1)

18(3/1)

14(2/1)

14(2/1)

14(2/1)

10(2/0)

10(2/0)

–(An) 24(5/1)

20(4/1)

22(4/1)

20(4/1)

16(3/1)

16(3/1)

16(3/1)

12(3/0)

12(3/0)

(d 16, An) 26(5/1)

22(4/1)

24(4/1)

22(4/1)

18(3/1)

18(3/1)

18(3/1)

14(3/0)

14(3/0)

(d 8, An, Xn)* 24(5/1)

20(4/1)

22(4/1)

20(4/1)

16(3/1)

16(3/1)

16(3/1)

12(3/0)

12(3/0)

(xxx).W 28(6/1)

24(5/1)

26(5/1)

24(5/1)

20(4/1)

20(4/1)

20(4/1)

16(4/0)

16(4/0)

(xxx).L 24(5/1)

20(4/1)

22(4/1)

20(4/1)

16(3/1)

16(3/1)

16(3/1)

12(3/0)

12(3/0)

(d 16, PC) 26(5/1)

22(4/1)

24(4/1)

22(4/1)

18(3/1)

18(3/1)

18(3/1)

14(3/0)

14(3/0)

(d 8, PC, Xn)* 20(4/1)

16(3/1)

18(3/1)

16(3/1)

12(2/1)

12(2/1)

12(2/1)

8(2/0)

8(2/0)

#<data>

*The size of the index register (Xn) does not affect execution time.

Table 9-3. Move Byte and Word Instruction Loop Mode Execution Times

Loop Continued Loop Terminated

Valid Count, cc False Valid count, cc True Expired Count

Destination

Source (An) (An)+ –(An) (An) (An)+ –(An) (An) (An)+ –(An)

—

16(2/1)

16(2/1)

—

18(2/1)

18(2/1)

—

10(0/1)

10(0/1)

Dn —

16(2/1)

16(2/1)

—

18(2/1)

18(2/1)

—

10(0/1)

10(0/1)

An* 20(3/1)

18(3/1)

18(3/1)

22(3/1)

20(3/1)

20(3/1)

16(1/1)

14(1/1)

14(1/1)

(An)

(An)+ 14(1/1) 14(1/1) 16(1/1) 20(3/1) 20(3/1) 22(3/1) 18(3/1) 18(3/1) 20(3/1)

–(An) 16(1/1) 16(1/1) 18(1/1) 22(3/1) 22(3/1) 24(3/1) 20(3/1) 20(3/1) 22(3/1)

*Word only.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 9-3

Table 9-4. Move Long Instruction Execution Times

Destination

Source Dn An (An) (An)+ –(An) (d16, An) (d8, An, Xn)* (xxx).W (xxx).L

20(3/2)

16(2/2)

18(2/2)

16(2/2)

14(1/2)

12(1/2)

12(1/2)

4(1/0)

4(1/0)

Dn 20(3/2)

16(2/2)

18(2/2)

16(2/2)

14(1/2)

12(1/2)

12(1/2)

4(1/0)

4(1/0)

An 28(5/2)

24(4/2)

26(4/2)

24(4/2)

20(3/2)

20(3/2)

20(3/2)

12(3/0)

12(3/0)

(An) 28(5/2)

24(4/2)

26(4/2)

24(4/2)

20(3/2)

20(3/2)

20(3/2)

12(3/0)

12(3/0)

(An)+ 30(5/2)

26(4/2)

28(4/2)

26(4/2)

22(3/2)

22(3/2)

22(3/2)

14(3/0)

14(3/0)

–(An) 32(6/2)

28(5/2)

30(5/2)

28(5/2)

24(4/2)

24(4/2)

24(4/2)

16(4/0)

16(4/0)

(d 16, An) 34(6/2)

30(5/2)

32(5/2)

30(5/2)

26(4/2)

26(4/2)

26(4/2)

18(4/0)

18(4/0)

(d 8, An, Xn)* 32(6/2)

28(5/2)

30(5/2)

28(5/2)

24(4/2)

24(4/2)

24(4/2)

16(4/0)

16(4/0)

(xxx).W 36(7/2)

32(6/2)

34(6/2)

32(6/2)

28(5/2)

28(5/2)

28(5/2)

20(5/0)

20(5/0)

(xxx).L 32(5/2)

28(5/2)

30(5/2)

28(5/2)

24(4/2)

24(4/2)

24(4/2)

16(4/0)

16(4/0)

(d 16, PC) 34(6/2)

30(5/2)

32(5/2)

30(5/2)

26(4/2)

26(4/2)

26(4/2)

18(4/0)

18(4/0)

(d 8, PC, Xn)* 28(5/2)

24(4/2)

26(4/2)

24(4/2)

20(3/2)

20(3/2)

20(3/2)

12(3/0)

12(3/0)

#<data>

*The size of the index register (Xn) does not affect execution time.

Table 9-5. Move Long Instruction Loop Mode Execution Times

Loop Continued Loop Terminated

Valid Count, cc False Valid count, cc True Expired Count

Destination

Source (An) (An)+ –(An) (An) (An)+ –(An) (An) (An)+ –(An)

—

18(2/2)

18(2/2)

—

20(2/2)

20(2/2)

—

14(0/2)

14(0/2)

Dn —

18(2/2)

18(2/2)

—

20(2/2)

20(2/2)

—

14(0/2)

14(0/2)

An 26(4/2)

24(4/2)

24(4/2)

30(4/2)

28(4/2)

28(4/2)

24(2/2)

22(2/2)

22(2/2)

(An)

(An)+ 22(2/2) 22(2/2) 24(2/2) 28(4/2) 28(4/2) 30(4/2) 24(4/2) 24(4/2) 26(4/2)

–(An) 24(2/2) 24(2/2) 26(2/2) 30(4/2) 30(4/2) 32(4/2) 26(4/2) 26(4/2) 28(4/2)

9.3 STANDARD INSTRUCTION EXECUTION TIMES

The numbers of clock periods shown in tables 9-6 and 9-7 indicate the times required to

perform the operations, store the results, and read the next instruction. The total number

of clock periods, the number of read cycles, and the number of write cycles are shown in

the previously described format. The number of clock periods, the number of read cycles,

and the number of write cycles, respectively, must be added to those of the effective

address calculation where indicated by a plus sign (+).

In Tables 9-6 and 9-7, the following notation applies:

An — Address register operand

Sn — Data register operand

ea — An operand specified by an effective address

M — Memory effective address operand

9-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 9-6. Standard Instruction Execution Times

Instruction Size op<ea>, An*** op<ea>, Dn op Dn, <M>

ADD/ADDA Byte, Word 8(1/0)+ 4(1/0)+ 8(1/1)+

Long 6(1/0)+ 6(1/0)+ 12(1/2)+

AND Byte, Word — 4(1/0)+ 8(1/1)+

Long — 6(1/0)+ 12(1/2)+

CMP/CMPA Byte, Word 6(1/0)+ 4(1/0)+ —

Long 6(1/0)+ 6(1/0)+ —

DIVS — — 122(1/0)+ —

DIVU — — 108(1/0)+ —

EOR Byte, Word — 4(1/0)** 8(1/1)+

Long — 6(1/0)** 12(1/2)+

MULS/MULU — — 42(1/0)+* —

— — 40(1/0)* —

OR Byte, Word — 4(1/0)+ 8(1/1)+

Long — 6(1/0)+ 12(1/2)+

SUB/SUBA Byte, Word 8(1/0)+ 4(1/0)+ 8(1/1)+

Long 6(1/0)+ 6(1/0)+ 12(1/2)+

+ Add effective address calculation time.

* Indicates maximum value.

** Only available address mode is data register direct.

*** Word or long word only.

Table 9-7 Standard Instruction Loop Mode Execution Times

Loop Continued Loop Terminated

Valid Count cc False Valid Count cc True Expired Count

op<ea>, op<ea>, op Dn, op<ea>, op<ea>, op Dn, op<ea>, op<ea>, op Dn,

Instruction Size An* Dn <ea> An* Dn <ea> An* Dn <ea>

ADD Byte, 18(1/0) 16(1/0) 16(1/1) 24(3/0) 22(3/0) 22(3/1) 22(3/0) 20(3/0) 20(3/1)

Word

Long 22(2/0) 22(2/0) 24(2/2) 28(4/0) 28(4/0) 30(4/2) 26(4/0) 26(4/0) 28(4/2)

AND Byte, — 16(1/0) 16(1/1) — 22(3/0) 22(3/1) — 20(3/0) 20(3/1)

Word

Long — 22(2/0) 24(2/2) — 28(4/0) 30(4/2) — 26(4/0) 28(4/2)

CMP Byte, 12(1/0) 12(1/0) — 18(3/0) 18(3/0) — 16(3/0) 16(4/0) —

Word

Long 18(2/0) 18(2/0) — 24(4/0) 24(4/0) — 20(4/0) 20(4/0) —

EOR Byte, — — 16(1/0) — — 22(3/1) — — 20(3/1)

Word

Long — — 24(2/2) — — 30(4/2) — — 28(4/2)

OR Byte, — 16(1/0) 16(1/0) — 22(3/0) 22(3/1) — 20(3/0) 20(3/1)

Word

Long — 22(2/0) 24(2/2) — 28(4/0) 30(4/2) — 26(4/0) 28(4/2)

SUB Byte, 18(1/0) 16(1/0) 16(1/1) 24(3/0) 22(3/0) 22(3/1) 22(3/0) 20(3/0) 20(3/1)

Word

Long 22(2/0) 20(2/0) 24(2/2) 28(4/0) 26(4/0) 30(4/2) 26(4/0) 24(4/0) 28(4/2)

*Word or long word only.

<ea> may be (An), (An)+, or –(An) only. Add two clock periods to the table value if <ea> is –(An).

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 9-5

9.4 IMMEDIATE INSTRUCTION EXECUTION TIMES

The numbers of clock periods shown in Table 9-8 include the times to fetch immediate

operands, perform the operations, store the results, and read the next operation. The total

number of clock periods, the number of read cycles, and the number of write cycles are

shown in the previously described format. The number of clock periods, the number of

read cycles, and the number of write cycles, respectively, must be added to those of the

effective address calculation where indicated by a plus sign (+).

In Tables 9-8, the following notation applies:

# — Immediate operand

Dn — Data register operand

An — Address register operand

M — Memory operand

Table 9-8. Immediate Instruction Execution Times

Instruction Size op #, Dn op #, An op #, M

ADDI Byte, Word 8(2/0) — 12(2/1)+

Long 14(3/0) — 20(3/2)+

ADDQ Byte, Word 4(1/0) 4(1/0)* 8(1/2)+

Long 8(1/0) 8(1/1) 12(1/2)+

ANDI Byte, Word 8(2/0) — 12(2/1)+

Long 14(3/0) — 20(3/1)+

CMPI Byte, Word 8(2/0) — 8(2/0)+

Long 12(3/0) — 12(3/0)+

EORI Byte, Word 8(2/0) — 12(2/1)+

Long 14(3/0) — 20(3/2)+

MOVEQ Long 4(1/0) — —

ORI Byte, Word 8(2/0) — 12(2/1)+

Long 14(3/0) — 20(3/2)+

SUBI Byte, Word 8(2/0) — 12(2/1)+

Long 14(3/0) — 20(3/2)+

SUBQ Byte, Word 4(1/0) 4(1/0)* 8(1/1)+

Long 8(1/0) 8(1/0) 12(1/2)+

+Add effective address calculation time.

*Word only.

9.5 SINGLE OPERAND INSTRUCTION EXECUTION TIMES

Tables 9-9, 9-10, and 9-11 list the timing data for the single operand instructions. The total

number of clock periods, the number of read cycles, and the number of write cycles are

shown in the previously described format. The number of clock periods, the number of

read cycles, and the number of write cycles, respectively, must be added to those of the

effective address calculation where indicated by a plus sign (+).

9-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 9-9. Single Operand Instruction

Execution Times

Instruction Size Register Memory

NBCD Byte 6(1/0) 8(1/1)+

NEG Byte, Word 4(1/0) 8(1/1)+

Long 6(1/0) 12(1/2)+

NEGX Byte, Word 4(1/0) 8(1/1)+

Long 6(1/0) 12(1/2)+

NOT Byte, Word 4(1/0) 8(1/1)+

Long 6(1/0) 12(1/2)+

Scc Byte, False 4(1/0) 8(1/1)+*

Byte, True 4(1/0) 8(1/1)+*

TAS Byte 4(1/0) 14(2/1)+*

TST Byte, Word 4(1/0) 4(1/0)+

Long 4(1/0) 4(1/0)+

+Add effective address calculation time.

*Use nonfetching effective address calculation time.

Table 9-10. Clear Instruction Execution Times

Size Dn An (An) (An)+ –(An) (d , An) (d 8, An, Xn)* (xxx).W (xxx).L

16

CLR Byte, Word 4(1/0) — 8(1/1) 8(1/1) 10(1/1) 12(2/1) 16(2/1) 12(2/1) 16(3/1)

Long 6(1/0) — 12(1/2) 12(1/2) 14(1/2) 16(2/2) 20(2/2) 16(2/2) 20(3/2)

*The size of the index register (Xn) does not affect execution time.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 9-7

Table 9-11. Single Operand Instruction Loop Mode Execution Times

Loop Continued Loop Terminated

Valid Count, cc False Valid Count, cc True Expired Count

Instruction Size (An) (An)+ –(An) (An) (An)+ –(An) (An) (An)+ –(An)

CLR Byte, 10(0/1) 10(0/1) 12(0/1) 18(2/1) 18(2/1) 20(2/0) 16(2/1) 16(2/1) 18(2/1)

Word

Long 14(0/2) 14(0/2) 16(0/2) 22(2/2) 22(2/2) 24(2/2) 20(2/2) 20(2/2) 22(2/2)

NBCD Byte 18(1/1) 18(1/1) 20(1/1) 24(3/1) 24(3/1) 26(3/1) 22(3/1) 22(3/1) 24(3/1)

NEG Byte, 16(1/1) 16(1/1) 18(2/2) 22(3/1) 22(3/1) 24(3/1) 20(3/1) 20(3/1) 22(3/1)

Word

Long 24(2/2) 24(2/2) 26(2/2) 30(4/2) 30(4/2) 32(4/2) 28(4/2) 28(4/2) 30(4/2)

NEGX Byte, 16(1/1) 16(1/1) 18(2/2) 22(3/1) 22(3/1) 24(3/1) 20(3/1) 20(3/1) 22(3/1)

Word

Long 24(2/2) 24(2/2) 26(2/2) 30(4/2) 30(4/2) 32(4/2) 28(4/2) 28(4/2) 30(4/2)

NOT Byte, 16(1/1) 16(1/1) 18(2/2) 22(3/1) 22(3/1) 24(3/1) 20(3/1) 20(3/1) 22(3/1)

Word

Long 24(2/2) 24(2/2) 26(2/2) 30(4/2) 30(4/2) 32(4/2) 28(4/2) 28(4/2) 30(4/2)

TST Byte, 12(1/0) 12(1/0) 14(1/0) 18(3/0) 18(3/0) 20(3/0) 16(3/0) 16(3/0) 18(3/0)

Word

Long 18(2/0) 18(2/0) 20(2/0) 24(4/0) 24(4/0) 26(4/0) 20(4/0) 20(4/0) 22(4/0)

9.6 SHIFT/ROTATE INSTRUCTION EXECUTION TIMES

Tables 9-12 and 9-13 list the timing data for the shift and rotate instructions. The total

number of clock periods, the number of read cycles, and the number of write cycles are

shown in the previously described format. The number of clock periods, the number of

read cycles, and the number of write cycles, respectively, must be added to those of the

effective address calculation where indicated by a plus sign (+).

Table 9-12. Shift/Rotate Instruction Execution Times

Instruction Size Register Memory*

ASR, ASL Byte, Word 6+2n (1/0) 8(1/1)+

Long 8+2n (1/0) —

LSR, LSL Byte, Word 6+2n (1/0) 8(1/1)+

Long 8+2n (1/0) —

ROR, ROL Byte, Word 6+2n (1/0) 8(1/1)+

Long 8+2n (1/0) —

ROXR, ROXL Byte, Word 6+2n (1/0) 8(1/1)+

Long 8+2n (1/0) —

+Add effective address calculation time.

n is the shift or rotate count.

* Word only.

9-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 9-13. Shift/Rotate Instruction Loop Mode Execution Times

Loop Continued Loop Terminated

Valid Count cc False Valid Count cc True Expired Count

Instruction Size (An) (An)+ –(An) (An) (An)+ –(An) (An) (An)+ –(An)

ASR, ASL Word 18(1/1) 18(1/1) 20(1/1) 24(3/1) 24(3/1) 26(3/1) 22(3/1) 22(3/1) 24(3/1)

LSR, LSL Word 18(1/1) 18(1/1) 20(1/1) 24(3/1) 24(3/1) 26(3/1) 22(3/1) 22(3/1) 24(3/1)

ROR, ROL Word 18(1/1) 18(1/1) 20(1/1) 24(3/1) 24(3/1) 26(3/1) 22(3/1) 22(3/1) 24(3/1)

ROXR, ROXL Word 18(1/1) 18(1/1) 20(1/1) 24(3/1) 24(3/1) 26(3/1) 22(3/1) 22(3/1) 24(3/1)

9.7 BIT MANIPULATION INSTRUCTION EXECUTION TIMES

Table 9-14 lists the timing data for the bit manipulation instructions. The total number of

clock periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

Table 9-14. Bit Manipulation Instruction Execution Times

Dynamic Static

Instruction Size Register Memory Register Memory

BCHG Byte — 8(1/1)+ — 12(2/1)+

Long 8(1/0)* — 12(2/0)* —

BCLR Byte — 10(1/1)+ — 14(2/1)+

Long 10(1/0)* — 14(2/0)* —

BSET Byte — 8(1/1)+ — 12(2/1)+

Long 8(1/0)* — 12(2/0)* —

BTST Byte — 4(1/0)+ — 8(2/0)+

Long 6(1/0)* — 10(2/0) —

+Add effective address calculation time.

* Indicates maximum value; data addressing mode only.

9.8 CONDITIONAL INSTRUCTION EXECUTION TIMES

Table 9-15 lists the timing data for the conditional instructions. The total number of clock

periods, the number of read cycles, and the number of write cycles are shown in the

previously described format.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 9-9

Table 9-15. Conditional Instruction Execution Times

Instruction Displacement Branch Taken Branch Not Taken

Bcc Byte 10(2/0) 6(1/0)

Word 10(2/0) 10(2/0)

BRA Byte 10(2/0) —

Word 10(2/0) —

BSR Byte 18(2/2) —

Word 18(2/2) —

DBcc cc true — 10(2/0)

cc false 10(2/0) 16(3/0)

9.9 JMP, JSR, LEA, PEA, AND MOVEM INSTRUCTION

EXECUTION TIMES

Table 9-16 lists the timing data for the jump (JMP), jump to subroutine (JSR), load

effective address (LEA), push effective address (PEA), and move multiple registers

(MOVEM) instructions. The total number of clock periods, the number of read cycles, and

the number of write cycles are shown in the previously described format.

Table 9-16. JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times

Instruction Size (An) (An)+ –(An) (d ,An) (d 8,An,Xn)+ (xxx) W (xxx).L (d PC) (d , PC, Xn)*

16 8 16

JMP — 8(2/0) — — 10 (2/0) 14 (3/0) 10 (2/0) 12 (3/0) 10 (2/0) 14 (3/0)

JSR — 16 (2/2) — — 18 (2/2) 22 (2/2) 18 (2/2) 20 (3/2) 18 (2/2) 22 (2/2)

LEA — 4(1/0) — — 8(2/0) 12 (2/0) 8(2/0) 12 (3/0) 8(2/0) 12 (2/0)

PEA — 12 (1/2) — — 16 (2/2) 20 (2/2) 16 (2/2) 20 (3/2) 16 (2/2) 20 (2/2)

MOVEM Word 12+4n 12+4n — 16+4n 18+4n 16+4n 20+4n 16+4n 18+4n

→

M R (3+n/0) (3+n/0) — (4+n/0) (4+n/0) (4+n/0) (5+n/0) (4+n/0) (4+n/0)

Long 24+8n 12+8n — 16+8n 18+8n 16+8n 20+8n 16+8n 18+8n

(3+2n/0) (3+2n/0) — (4+2n/0) (4+2n/0) (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0)

MOVEM Word 8+4n — 8+4n 12+4n 14+4n 12+4n 16+4n — —

→

R M (2/n) — (2/n) (3/n) (3/n) (3/n) (4/n) — —

Long 8+8n — 8+8n 12+8n 14+8n 12+8n 16+8n — —

(2/2n) — (2/2n) (3/2n) (3/2n) (3/2n) (4/2n) — —

MOVES Byte/ 18 (3/0) 20 (3/0) 20 (3/0) 20 (4/0) 24 (4/0) 20 (4/0) 24 (5/0)

→

M R Word

Long 22 (4/0) 24 (4/0) 24 (4/0) 24 (5/0) 28 (5/0) 24 (5/0) 28 (6/0)

MOVES Byte/ 18 (2/1) 20 (2/1) 20 (2/1) 20 (3/1) 24 (3/1) 20 (3/1) 24 (4/1)

→

R M Word

Long 22 (2/2) 24 (2/2) 24 (2/2) 24 (3/2) 28 (3/2) 24 (3/2) 28 (4/2)

n is the number of registers to move.

*The size of the index register (Xn) does not affect the instruction's execution time.

9.10 MULTIPRECISION INSTRUCTION EXECUTION TIMES

Table 9-17 lists the timing data for multiprecision instructions. The numbers of clock

periods include the times to fetch both operands, perform the operations, store the results,

9-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

and read the next instructions. The total number of clock periods, the number of read

cycles, and the number of write cycles are shown in the previously described format.

The following notation applies in Table 9-17:

Dn — Data register operand

M — Memory operand

Table 9-17. Multiprecision Instruction Execution Times

Loop Mode

Nonlooped Continued Terminated

Valid Count, Valid Count, Expired Count

cc False cc True

Instruction Size op Dn, Dn op M, M*

ADDX Byte, Word 4(1/0) 18(3/1) 22(2/1) 28(4/1) 26(4/1)

Long 6(1/0) 30(5/2) 32(4/2) 38(6/2) 36(6/2)

CMPM Byte, Word — 12(3/0) 14(2/0) 20(4/0) 18(4/0)

Long — 20(5/0) 24(4/0) 30(6/0) 26(6/0)

SUBX Byte, Word 4(1/) 18(3/1) 22(2/1) 28(4/1) 26(4/1)

Long 6(1/0) 30(5/2) 32(4/2) 38(6/2) 36(6/2)

ABCD Byte 6(1/0) 18(3/1) 24(2/1) 30(4/1) 28(4/1)

SBCD Byte 6(1/0) 18(3/1) 24(2/1) 30(4/1) 28(4/1)

*Source and destination ea are (An)+ for CMPM and –(An) for all others.

9.11 MISCELLANEOUS INSTRUCTION EXECUTION TIMES

Table 9-18 lists the timing data for miscellaneous instructions. The total number of clock

periods, the number of read cycles, and the number of write cycles are shown in the

previously described format. The number of clock periods, the number of read cycles, and

the number of write cycles, respectively, must be added to those of the effective address

calculation where indicated by a plus sign (+).

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 9-11

Table 9-18. Miscellaneous Instruction Execution Times →

Register→ Source**

Instruction Size Register Memory Destination** Register

ANDI to CCR — 16(2/0) — — —

ANDI to SR — 16(2/0) — — —

CHK — 8(1/0)+ — — —

EORI to CCR — 16(2/0) — — —

EORI to SR — 16(2/0) — — —

EXG — 6(1/0) — — —

EXT Word 4(1/0) — — —

Long 4(1/0) — — —

LINK — 16(2/2) — — —

MOVE from CCR — 4(1/0) 8(1/1)+* —

MOVE to CCR — 12(2/0) 12(2/0)+ — —

MOVE from SR — 4(1/0) 8(1/1)+* — —

MOVE to SR — 12(2/0) 12(2/0)+ — —

MOVE from USP — 6(1/0) — — —

MOVE to USP — 6(1/0) — — —

MOVEC — — — 10(2/0) 12(2/0)

MOVEP Word — — 16(2/2) 16(4/0)

Long — — 24(2/4) 24(6/0)

NOP — 4(1/0) — — —

ORI to CCR — 16(2/0) — — —

ORI to SR — 16(2/0) — — —

RESET — 130(1/0) — — —

RTD — 16(4/0) — — —

RTE Short 24(6/0) — — —

Long, Retry Read 112(27/10) — — —

Long, Retry Write 112(26/1) — — —

Long, No Retry 110(26/0) — — —

RTR — 20(5/0) — — —

RTS — 16(4/0) — — —

STOP — 4(0/0) — — —

SWAP — 4(1/0) — — —

TRAPV — 4(1/0) — — —

UNLK — 12(3/0) — — —

+Add effective address calculation time.

+Use nonfetching effective address calculation time.

**Source or destination is a memory location for the MOVEP instruction and a control register

for the MOVEC instruction.

9-12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

9.12 EXCEPTION PROCESSING EXECUTION TIMES

Table 9-19 lists the timing data for exception processing. The numbers of clock periods

include the times for all stacking, the vector fetch, and the fetch of the first instruction of

the handler routine. The total number of clock periods, the number of read cycles, and the

number of write cycles are shown in the previously described format. The number of clock

periods, the number of read cycles, and the number of write cycles, respectively, must be

added to those of the effective address calculation where indicated by a plus sign (+).

Table 9-19. Exception Processing

Execution Times

Exception

Address Error 126(4/26)

Breakpoint Instruction* 45(5/4)

Bus Error 126(4/26)

CHK Instruction** 44(5/4)+

Divide By Zero 42(5/4)+

Illegal Instruction 38(5/4)

Interrupt* 46(5/4)

MOVEC, Illegal Control Register** 46(5/4)

Privilege Violation 38(5/4)

Reset*** 40(6/0)

RTE, Illegal Format 50(7/4)

RTE, Illegal Revision 70(12/4)

Trace 38(4/4)

TRAP Instruction 38(4/4)

TRAPV Instruction 38(5/4)

+ Add effective address calculation time.

* The interrupt acknowledge and breakpoint cycles

are assumed to take four clock periods.

** Indicates maximum value.

*** Indicates the time from when and

RESET HALT

are first sampled as negated to when instruction

execution starts.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 9-13

SECTION 10

ELECTRICAL AND THERMAL CHARACTERISTICS

This section provides information on the maximum rating and thermal characteristics for

the MC68000, MC68HC000, MC68HC001, MC68EC000, MC68008, and MC68010.

10.1 MAXIMUM RATINGS

Rating Symbol Value Unit This device contains protective

circuitry against damage due to high

static voltages or electrical fields;

Supply Voltage VCC –0.3 to 7.0 V however, it is advised that normal

precautions be taken to avoid

Input Voltage Vin –0.3 to 7.0 V application of any voltages higher

°C than maximum-rated voltages to this

TA TL to TH

Maximum Operating high-impedance circuit. Reliability of

0 to 70

Temperature Range operation is enhanced if unused

inputs are tied to an appropriate

–40 to 85

Commerical Extended "C" Grade logic voltage level (e.g., either GND

0 to 85

Commerical Extended "I" Grade or V ).

CC

°C

Storage Temperature Tstg –55 to 150

10.2 THERMAL CHARACTERISTICS

Characteristic Symbol Value Symbol Value Rating

θ

θ °C/W

Thermal Resistance JC

JA 15*

30

Ceramic, Type L/LC 15

33

Ceramic, Type R/RC 15*

30

Plastic, Type P 25*

45*

Plastic, Type FN

*Estimated

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 10-1

10.3 POWER CONSIDERATIONS °C

The average die-junction temperature, TJ, in can be obtained from:

θ JA) (1)

TJ = T A+(PD •

where: °C

TA = Ambient Temperature, °C/W

θ J = Package Thermal Resistance, Junction-to-Ambient,

A

PD = PINT + PI/O

PINT = ICC VCC, Watts — Chip Internal Power

x

PI/O = Power Dissipation on Input and Output Pins — User Determined

For most applications, P I/O<PINT and can be neglected.

An appropriate relationship between P and T (if P is neglected) is:

D J I/O

°C)

PD = K÷(TJ + 273 (2)

Solving Equations (1) and (2) for K gives:

θ 2

JA • P (3)

K = P • (TA + 273°C) + D

D

where K is a constant pertaining to the particular part. K can be determined from equation

(3) by measuring P (at thermal equilibrium) for a known TA. Using this value of K, the

D

values of PD and T can be obtained by solving Equations (1) and (2) iteratively for any

J

value of T A.

The curve shown in Figure 10-1 gives the graphic solution to the above equations for the

°C

specified power dissipation of 1.5 W over the ambient temperature range of -55 to 125

°C/W.

°C θ J of 45 Ambient temperature is that of the still air

using a maximum A θ JA cause the curve to shift downward slightly; for

surrounding the device. Lower values of

°/W, °C.

θ JA of 40 the curve is just below 1.4 W at 25

instance, for θ JA) can be separated into two components,

The total thermal resistance of a package (

θ θ

J and CA, representing the barrier to heat flow from the semiconductor junction to the

C θ θ

JC ) and from the case to the outside ambient air ( CA). These

package (case) surface (

terms are related by the equation:

θ θ θ

J = JC + CA (4)

A

θ θ

J is device related and cannot be influenced by the user. However, CA is user

C

dependent and can be minimized by such thermal management techniques as heat sinks,

ambient air cooling, and thermal convection. Thus, good thermal management on the part

θ θ θ

CA so that J approximately equals ; JC .

of the user can significantly reduce A

θ θ

JC for J in equation 1 results in a lower semiconductor junction

Substitution of A

temperature.

10-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

Table 10-1 summarizes maximum power dissipation and average junction temperature

for the curve drawn in Figure 10-1, using the minimum and maximum values of ambient

θ θ

JC for JA (assuming good thermal

temperature for different packages and substituting

management). Table 10-2 provides the maximum power dissipation and average junction

temperature assuming that no thermal management is applied (i.e., still air).

NOTE

Since the power dissipation curve shown in Figure 10-1 is

negatively sloped, power dissipation declines as ambient

temperature increases. Therefore, maximum power

dissipation occurs at the lowest rated ambient temperature, but

the highest average junction temperature occurs at the

power dissipation is

maximum ambient temperature where

lowest.

2.2

2.0

WATTS 1.8 16.6

), 7 MH

D

(P z

1.6

POWER 8, 1 0, 1 2.5

1.4 MH z

1.2

1.0

- 55 - 40 0 25 70 85 110 125

AMBIENT TEMPERATURE (T ), C

A

Figure 10-1. MC68000 Power Dissipation (PD ) vs Ambient Temperature (T A)

(Not Applicable to MC68HC000/68HC001/68EC000)

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 10-3

Table 10-1. Power Dissipation and Junction Temperature vs Temperature

(θJ C=θJ A)

θ

Package TA Range J PD (W) TJ (°C) PD (W) TJ (°C)

C

(°C/W) @ T Min. @ T Min. @ T Max. @ T Max.

A A A A

88

1.2

23

1.5

15

L/LC 0°C to 70°C 103

1.2

-14

1.7

15

-40°C to 85°C 103

1.2

23

1.5

15

0°C to 85°C

P 0°C to 70°C 15 1.5 23 1.2 88

88

1.2

23

1.5

15

R/RC 0°C to 70°C 103

1.2

-14

1.7

15

-40°C to 85°C 103

1.2

23

1.5

15

0°C to 85°C

FN 0°C to 70°C 25 1.5 38 1.2 101

NOTE: Table does not include values for the MC68000 12F.

Does not apply to the MC68HC000, MC68HC001, and MC68EC000.

Table 10-2. Power Dissipation and Junction Temperature vs Temperature

≠

θ θ

J J )

( C C

θ

Package TA Range J PD (W) TJ (°C) PD (W) TJ (°C)

A

(°C/W) @ T Min. @ T Min. @ T Max. @ T Max.

A A A A

88

1.2

23

1.5

30

L/LC 0°C to 70°C 103

1.2

-14

1.7

30

-40°C to 85°C 103

1.2

23

1.5

30

0°C to 85°C

P 0°C to 70°C 30 1.5 23 1.2 88

88

1.2

23

1.5

33

R/RC 0°C to 70°C 103

1.2

-14

1.7

33

-40°C to 85°C 103

1.2

23

1.5

33

0°C to 85°C

FN 0°C to 70°C 40 1.5 38 1.2 101

NOTE: Table does not include values for the MC68000 12F.

Does not apply to the MC68HC000, MC68HC001, and MC68EC000.

Values for thermal resistance presented in this manual, unless estimated, were derived

using the procedure described in Motorola Reliability Report 7843 “Thermal Resistance

Measurement Method for MC68XXX Microcomponent Devices”’ and are provided for

design purposes only. Thermal measurements are complex and dependent on procedure

and setup. User-derived values for thermal resistance may differ.

10.4 CMOS CONSIDERATIONS

The MC68HC000, MC68HC001, and MC68EC000, with it significantly lower power

consumption, has other considerations. The CMOS cell is basically composed of two

complementary transistors (a P channel and an N channel), and only one transistor is

turned on while the cell is in the steady state. The active P-channel transistor sources

current when the output is a logic high and presents a high impedance when the output is

logic low. Thus, the overall result is extremely low power consumption because no power

10-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA