Motorola 68000 - Microprocessors User’s Manual

Bus Arbitration Unit State Diagrams

RGTR RSTATE 0 GTRGT STATE 4STATE 1X GT XSTATE 3GTSTATE 2 R(b) 2-Wire Bus ArbitrationR Notes:1. State machine will not change ifR = Bus Request Internal the bus is S0 or S1. Refer toA = Bus Grant Acknowledge Internal 5.2.3.BUS ARBITRATION CONTROL.G = Bus Grant 2. The address bus will be placed inT = Three-state Control to Bus Control Logic the high-impedance state if T isX = Don't Care asserted and is negated.ASFigure 5-18. Bus Arbitration Unit State DiagramsFigures 5-19, 5-20, and 5-21 applies to all processors using 3-wire bus arbitration. Figures5-22, 5-23, and 5-24 applies to all processors using 2-wire bus arbitration.MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-17BUS THREE-STATED BUS RELEASED FROM THREE STATE ANDBG ASSERTED PROCESSOR STARTS NEXT BUS CYCLEBR VALID INTERNAL BGACK NEGATED INTERNALBR SAMPLED BGACK SAMPLEDBR ASSERTED BGACK NEGATEDCLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0

S1BRBGBGACKFC2–FC0A23–A1ASUDSLDSR/WDTACKD15–D0 PROCESSOR ALTERNATE BUS MASTER PROCESSOR

5-18 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA

BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE

BGACK NEGATED

BG ASSERTED AND BUS THREE STATED

BR VALID INTERNAL

BR SAMPLED

BR ASSERTED

CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4

BRBGBGACKFC2–FC0A23–A1ASUDSLDSR/WDTACKD15–D0 BUS

PROCESSOR INACTIVE ALTERNATE BUS MASTER PROCESSOR

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-19

BUS THREE-STATED BUS RELEASED FROM THREE STATE AN

BG ASSERTED PROCESSOR STARTS NEXT BUS CYCLE

BR VALID INTERNAL BGACK NEGATED INTERNAL

BR SAMPLED BGACK SAMPLED

BR ASSERTED BGACK NEGATED

CLK S0 S2 S4 S6 S0 S2 S4 S6 S0

BRBGBGACKFC2–FC0A23–A1ASUDSLDSR/WDTACKD15–D0 PROCESSOR ALTERNATE BUS MASTER

<h2>PROCESSORFigure 5-21. 3-Wire Bus Arbitration Timing Diagram—Special Case</h2>
<p>5-20 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA</p>
<p>BUS THREE-STATED BUS RELEASED FROM THREE STATE AND BG ASSERTED PROCESSOR STARTS NEXT BUS CYCLE</p>
<p>BR VALID INTERNAL BR NEGATED INTERNAL</p>
<p>BR SAMPLED BR SAMPLED</p>
<p>BR ASSERTED BR NEGATED</p>
<p>CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1</p>
<p>BRBGBGACKFC2–FC0A23–A1ASUDSLDSR/WDTACKD15–D0 ALTERNATE BUS MASTER PROCESSOR</p>

<h2>PROCESSORFigure 5-22. 2-Wire Bus Arbitration Timing Diagram—Processor Active</h2>
<p>MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL</p>
<p>BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE</p>
<p>BR NEGATED BG ASSERTED AND BUS THREE STATED</p>
<p>BR VALID INTERNAL</p>
<p>BR SAMPLED</p>
<p>BR ASSERTED</p>
<p>CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4</p>
<p>BRBGBGACKFC2–FC0A23–A1ASUDSLDSR/WDTACKD15–D0 BUS ALTERNATE BUS MASTER PROCESSOR</p>

<h2>PROCESSOR INACTIVEFigure 5-23. 2-Wire Bus Arbitration Timing Diagram—Bus Inactive</h2>
<p>5-22</p>

M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLABUS THREE-STATED BUS RELEASED FROM THREE STATE ANDBG ASSERTED PROCESSOR STARTS NEXT BUS CYCLEBR VALID INTERNAL BR NEGATED INTERNALBR SAMPLED BR SAMPLEDBR ASSERTED BR NEGATEDCLK S0 S2 S4 S6 S0 S2 S4 S6 S0BRBGBGACKFC2-FC0A23-A1ASUDSLDSR/WDTACKD15-D0 ALTERNATE BUS MASTER PROCESSORPROCESSORFigure 5-24. 2-Wire Bus Arbitration Timing Diagram—Special Case5.4. BUS ERROR AND HALT OPERATIONIn a bus architecture that requires a handshake from an external device, such as theasynchronous bus used in the M68000 Family, the handshake may not always occur. Abus error input is provided to terminate a bus cycle in error when the expected signal isnot asserted. Different systems and different devices within the same system requiredifferent maximum-response times. External circuitry can be provided to assert the buserror signal after the appropriate delay following the assertion of address strobe.In a virtual memory system,

are negated and is asserted. In the MC68010, a late bus error isDTACK HALT BERRalso recognized when is negated, and and are asserted within oneHALT DTACK BERRclock cycle.

When the bus error condition is recognized, the current bus cycle is terminated in S9 for aread cycle, a write cycle, or the read portion of a read-modify-write cycle. For the writeportion of a read-modify-write cycle, the current bus cycle is terminated in S21. As long asremains asserted, the data and address buses are in the high-impedance state.BERR

Figure 5-25 shows the timing for the normal bus error, and Figure 5-26 shows the timingfor the MC68010 late bus error.

S0 S2 S4 w w ww S6 S8CLKFC2–FC0A23–A1ASLDS/UDSR/WDTACKD15–D0BERRHALT INITIATE INITIATE BUSRESPONSE BUS ERRORREAD FAILURE DETECTION ERROR STACKINGFigure 5-25. Bus Error Timing Diagram5-24 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLAS0 S2 S4 S6CLKFC2–FC0A23–A1ASUDS/LDSR/WDTACKD15–D0BERRHALT BUS ERROR

After the aborted bus cycle is terminated and is negated, the processor enters BERR exception processing for the bus error exception. During the exception processing sequence, the following information is placed on the supervisor stack:

1. Status register
2. Program counter (two words, which may be up to five words past the instruction being executed)
3. Error information

The first two items are identical to the information stacked by any other exception. The error information differs for the MC68010. The MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008 stack bus error information to help determine and to correct the error. The MC68010 stacks the frame format and the vector offset followed by 22 words of internal register information. The return from exception (RTE) instruction restores the internal register information so that the MC68010 can continue execution of the instruction after the

error handler routine completes. After the processor has placed the required information on the stack, the bus error exception vector is read from vector table entry 2 (offset $08) and placed in the program counter. The processor resumes execution at the address in the vector, which is the first instruction in the bus error handler routine.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-25

NOTE
In the MC68010, if a read-modify-write operation terminates in a bus error, the processor reruns the entire read-modify-write operation when the RTE instruction at the end of the bus error handler returns control to the instruction in error. The processor reruns the entire operation whether the error occurred during the read or write portion.

5.4.2 Retrying The Bus Cycle
The assertion of the bus error signal during a bus cycle in which is also asserted by HALTan external device initiates a retry operation. Figure 5-27 is a timing diagram of the retry operation. The delayed signal in the

MC68010 also initiates a retry operation when BERR is asserted by an external device. Figure 5-28 shows the timing of the delayed HALT operation.

The processor terminates the bus cycle, then puts the address and data lines in the high-impedance state. The processor remains in this state until BERR is negated. Then the HALT processor retries the preceding cycle using the same function codes, address, and data (for a write operation). BERR should be negated at least one clock cycle before HALT is negated.

NOTE: To guarantee that the entire read-modify-write cycle runs correctly and that the write portion of the operation...

isperformed without negating the address strobe, the processor does not retry a read-modify-write cycle. When a bus error occurs during a read-modify-write operation, a bus error operation is performed whether or not is asserted.

5.4.3 Halt Operation (performs a halt/run/single-step operation similar to the halt operation of an HALTMC68000. When is asserted by an external device, the processor halts and remains HALThalted as long as the signal remains asserted, as shown in Figure 5-29.

MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-27

S0 S2 S4 S6 S0 S2 S4 S6

CLK FC2–FC0 A23–A1 ASUDSLDS R/W DTACK D0–D15 BERR HALT RETRY READ HA