Motorola 68000 - Microprocessors User’s Manual

Microprocessors User’s Manual

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Table of contents

• Section 1: Overview
  • 1.1 MC68000 ....................................................................................... 1-1
  • 1.2 MC68008 ....................................................................................... 1-2
  • 1.3 MC68010 ....................................................................................... 1-2
  • 1.4 MC68HC000 ................................................................................. 1-2
  • 1.5 MC68HC001 ................................................................................. 1-3
  • 1.6 MC68EC000 ................................................................................. 1-3
• Section 2: Introduction
  • 2.1 Programmer's Model ....................................................................... 2-1
  • 2.1.1 User's Programmer's Model ......................................................... 2-1
  • 2.1.2 Supervisor Programmer's Model .................................................. 2-2
  • 2.1.3 Status Register ......................................................................... 2-3
  • 2.2 Data Types and Addressing Modes ........................................... 2-3
  • 2.3 Data Organization In Registers .................................................... 2-5
  • 2.3.1 Data Registers .......................................................................... 2-5
  • 2.3.2 Address Registers ...................................................................... 2-6
  • 2.4 Data Organization In Memory ..................................................... 2-6
  • 2.5 Instruction Set Summary ............................................................ 2-8
• Section 3: Signal Description
  • 3.1 Address Bus .................................................................................. 3-3
  • 3.2 Data Bus ......................................................................................... 3-4
  • 3.3 Asynchronous Bus Control ......................................................... 3-4
  • 3.4 Bus Arbitration Control ................................................................ 3-5
  • 3.5 Interrupt Control ........................................................................... 3-6
  • 3.6 System Control ............................................................................. 3-7
  • 3.7 M6800 Peripheral Control ............................................................... 3-8
  • 3.8 Processor Function Codes .......................................................... 3-8
  • 3.9 Clock ........................................................................................... 3-9
  • 3.10 Power Supply .............................................................................. 3-9
  • 3.11 Signal Summary .......................................................................... 3-10
• Section 4: 8-Bit Bus Operations
  • 4.1 Data Transfer Operations ............................................................ 4-1
  • 4.1.1 Read Operations ...................................................................... 4-1
  • 4.1.2 Write Cycle .............................................................................. 4-3
  • 4.1.3 Read-Modify-Write Cycle ............................................................. 4-5
  • 4.2 Other Bus Operations ................................................................. 4-8
• Section 5: 16-Bit Bus Operations
  • 5.1 Data Transfer Operations ............................................................ 5-1
  • 5.1.1 Read Operations ...................................................................... 5-1
  • 5.1.2 Write Cycle .............................................................................. 5-4
  • 5.1.3 Read-Modify-Write Cycle ............................................................. 5-7
  • 5.1.4 CPU Space Cycle .................................................................. 5-9
  • 5.2 Bus Arbitration .............................................................................. 5-11
  • 5.2.1 Requesting The Bus ................................................................. 5-14
  • 5.2.2 Receiving The Bus Grant .......................................................... 5-15
  • 5.2.3 Acknowledgment of Mastership (3-Wire Arbitration Only) ............ 5-15
  • 5.3 Bus Arbitration Control ................................................................. 5-15
  • 5.4 Bus Error and Halt Operation ........................................................ 5-23
  • 5.4.1 Bus Error Operation ................................................................. 5-24
  • 5.4.2 Retrying The Bus Cycle ............................................................ 5-26
  • 5.4.3 Halt Operation ........................................................................ 5-27
  • 5.4.4 Double Bus Fault ................................................................... 5-28
  • 5.5 Reset Operation .......................................................................... 5-29
  • 5.6 The Relationship of DTACK, BERR, HALT ................................. 5-30
  • 5.7 Asynchronous Operation ............................................................. 5-32
  • 5.8 Synchronous Operation ............................................................... 5-35
• Section 6: Exception Processing
  • 6.1 Privilege Modes .......................................................................... 6-1
  • 6.1.1 Supervisor Mode .................................................................. 6-2
  • 6.1.2 User Mode ............................................................................ 6-2
  • 6.1.3 Privilege Mode Changes ............................................................ 6-2
  • 6.1.4 Reference Classification ............................................................ 6-3
  • 6.2 Exception Processing .................................................................... 6-4
  • 6.2.1 Exception Vectors ................................................................. 6-4
  • 6.2.2 Kinds Of Exceptions ................................................................. 6-5
  • 6.2.3 Multiple Exceptions .................................................................. 6-8
  • 6.2.4 Exception Stack Frames ........................................................... 6-9
  • 6.2.5 Exception Processing Sequence .............................................. 6-11
  • 6.3 Processing of Specific Exceptions ................................................ 6-11
  • 6.3.1 Reset ..................................................................................... 6-11
  • 6.3.2 Interrupts ............................................................................... 6-12
  • 6.3.3 Uninitialized Interrupt .............................................................. 6-13
  • 6.3.4 Spurious Interrupt ................................................................ 6-13
  • 6.3.5 Instruction Traps .................................................................. 6-13
  • 6.3.6 Illegal and Unimplemented Instructions ................................... 6-14
  • 6.3.7 Privilege Violations ................................................................. 6-15
  • 6.3.8 Tracing .................................................................................. 6-15
  • 6.3.9 Bus Errors ............................................................................ 6-16
  • 6.3.9.1 Bus Error ......................................................................... 6-16
  • 6.3.9.2 Bus Error (MC68010) ............................................................ 6-17
  • 6.3.10 Address Error ......................................................................... 6-19
  • 6.4 Return From Exception (MC68010) ............................................... 6-20
• Section 7: 8-Bit Instruction Timing
  • 7.1 Operand Effective Address Calculation Times ................................ 7-1
  • 7.2 Move Instruction Execution Times ................................................ 7-2
  • 7.3 Standard Instruction Execution Times ........................................... 7-3
  • 7.4 Immediate Instruction Execution Times ......................................... 7-4
  • 7.5 Single Operand Instruction Execution Times .................................. 7-5
  • 7.6 Shift/Rotate Instruction Execution Times ........................................ 7-6
  • 7.7 Bit Manipulation Instruction Execution Times ................................. 7-7
  • 7.8 Conditional Instruction Execution Times ......................................... 7-7
  • 7.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times .... 7-8
  • 7.10 Multiprecision Instruction Execution Times .................................. 7-8
  • 7.11 Miscellaneous Instruction Execution Times ................................. 7-9
  • 7.12 Exception Processing Instruction Execution Times ..................... 7-10
• Section 8: 16-Bit Instruction Timing
  • 8.1 Operand Effective Address Calculation Times ................................ 8-1
  • 8.2 Move Instruction Execution Times ................................................. 8-2
  • 8.3 Standard Instruction Execution Times ........................................... 8-3
  • 8.4 Immediate Instruction Execution Times ......................................... 8-4
  • 8.5 Single Operand Instruction Execution Times .................................. 8-5
  • 8.6 Shift/Rotate Instruction Execution Times ........................................ 8-6
  • 8.7 Bit Manipulation Instruction Execution Times ................................. 8-7
  • 8.8 Conditional Instruction Execution Times ......................................... 8-7
  • 8.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times .... 8-8
  • 8.10 Multiprecision Instruction Execution Times .................................. 8-8
  • 8.11 Miscellaneous Instruction Execution Times ................................. 8-9
  • 8.12 Exception Processing Instruction Execution Times ..................... 8-10
• Section 9: MC68010 Instruction Timing
  • 9.1 Operand Effective Address Calculation Times ................................ 9-2
  • 9.2 Move Instruction Execution Times ................................................. 9-2
  • 9.3 Standard Instruction Execution Times ........................................... 9-4
  • 9.4 Immediate Instruction Execution Times ......................................... 9-6
  • 9.5 Single Operand Instruction Execution Times .................................. 9-6
  • 9.6 Shift/Rotate Instruction Execution Times ........................................ 9-8
  • 9.7 Bit Manipulation Instruction Execution Times ................................. 9-9
  • 9.8 Conditional Instruction Execution Times ......................................... 9-9
  • 9.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times .... 9-10
  • 9.10 Multiprecision Instruction Execution Times .................................. 9-11
  • 9.11 Miscellaneous Instruction Execution Times ................................. 9-11
  • 9.12 Exception Processing Instruction Execution Times ..................... 9-13
• Section 10: Electrical and Thermal Characteristics
  • 10.1 Maximum Ratings ......................................................................... 10-1
  • 10.2 Thermal Characteristics ................................................................. 10-1
  • 10.3 Power Considerations .................................................................. 10-2
  • 10.4 CMOS Considerations .................................................................. 10-4
  • 10.5 AC Electrical Specifications Definitions ........................................... 10-5
  • 10.6 MC68000/68008/68010 DC Electrical Characteristics .................. 10-7
  • 10.7 DC Electrical Characteristics .......................................................... 10-8
  • 10.8 AC Electrical Specifications—Clock Timing .................................. 10-8
  • 10.9 MC68008 AC Electrical Specifications—Clock Timing ................... 10-9
  • 10.10 AC Electrical Specifications—Read and Write Cycles .................. 10-10
  • 10.11 AC Electrical Specifications—MC68000 To M6800 Peripheral ....... 10-15
  • 10.12 AC Electrical Specifications—Bus Arbitration .............................. 10-17
  • 10.13 MC68EC000 DC Electrical Specifications ................................ 10-23
  • 10.14 MC68EC000 AC Electrical Specifications—Read and Write .......... 10-24
  • 10.15 MC68EC000 AC Electrical Specifications—Bus Arbitration .......... 10-28
• Section 11: Ordering Information and Mechanical Data
  • 11.1 Pin Assignments ............................................................................ 11-1
  • 11.2 Package Dimensions ..................................................................... 11-7
• Appendix A: MC68010 Loop Mode Operation
• Appendix B: M6800 Peripheral Interface
  • B.1 Data Transfer Operation ................................................................. B-1
  • B.2 Interrupt Interface Operation ........................................................ B-4

List of illustrations

• Figure 2-1 User Programmer's Model ................................................................ 2-2
• Figure 2-2 Supervisor Programmer's Model Supplement ....................................... 2-2
• Figure 2-3 Supervisor Programmer's Model Supplement (MC68010) ......................... 2-3
• Figure 2-4 Status Register ................................................................................ 2-3
• Figure 2-5 Word Organization In Memory ................................................................. 2-6
• Figure 2-6 Data Organization In Memory ................................................................. 2-7
• Figure 2-7 Memory Data Organization (MC68008) .................................................... 2-3
• Figure 3-1 Input and Output Signals (MC68000, MC68HC000, MC68010) .............. 3-1
• Figure 3-2 Input and Output Signals (MC68HC001) ................................................. 3-2
• Figure 3-3 Input and Output Signals (MC68EC000) ................................................ 3-2
• Figure 3-4 Input and Output Signals (MC68008 48-Pin Version) ............................. 3-3
• Figure 3-5 Input and Output Signals (MC68008 52-Pin Version) ............................. 3-3
• Figure 4-1 Byte Read-Cycle Flowchart...................................................................... 4-2
• Figure 4-2 Read and Write-Cycle Timing Diagram ................................................... 4-2
• Figure 4-3 Byte Write-Cycle Flowchart ...................................................................... 4-4
• Figure 4-4 Write-Cycle Timing Diagram .................................................................