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Motorola 68000 - Instruction set Appunti scolastici Premium

Appunti in inglese di Architetture Sistemi Elaborazione del prof. Mazzocca su Motorola 68000 - Instruction set: ABCD (Add decimal with extend), ADD (Add binary), ADDA (Add address), ADDI (Add immediate), ADDQ (Add quick), ADDX (Add extended), AND logical, ASL, ASR (Arithmetic shift left/right)

Esame di Architetture Sistemi Elaborazione docente Prof. N. Mazzocca

Anteprima

ESTRATTO DOCUMENTO

The 68000's Instruction Set

2 Two notations are employed for address register indirect addressing. The

notation originally used to indicate address register indirect addressing has been

superseded. However, the Teesside 68000 simulator supports only the older form.

Old notation Current notation

d(An), d(An,Xi) (d,An), (d,An,Xi)

d(PC), d(PC,Xi) (d,PC), (d,PC,Xi)

ABCD Add decimal with extend

Operation: [destination] [source] + [destination] + [X]

10 10 10

Syntax: ABCD Dy,Dx

ABCD -(Ay),-(Ax)

Attributes: Size = byte

Description: Add the source operand to the destination operand along with

the extend bit, and store the result in the destination location.

The addition is performed using BCD arithmetic. The only legal

addressing modes are data register direct and memory to memory

with address register indirect using pre-decrementing.

Application: The instruction is used in chain arithmetic to add together

ABCD

strings of BCD digits. Consider the addition of two nine-digit

numbers. Note that the strings are stored so that the least-

significant digit is at the high address.

LEA Number1,A0 A0 points at first string

LEA Number2,A1 A1 points at second string

MOVE #8,D0 Nine digits to add

MOVE #$04,CCR Clear X-bit and Z-bit of the CCR

LOOP ABCD -(A0),-(A1) Add a pair of digits

DBRA D0,LOOP Repeat until 9 digits added

Condition codes: X N Z V C

* U * U *

The Z-bit is cleared if the result is non-zero, and left unchanged

otherwise. The Z-bit is normally set by the programmer before

the BCD operation, and can be used to test for zero after a chain

of multiple-precision operations. The C-bit is set if a decimal

carry is generated.

The 68000's Instruction Set 3

ADD Add binary

Operation: [destination] [source] + [destination]

Syntax: ADD <ea>,Dn

ADD Dn,<ea>

Attributes: Size = byte, word, longword

Description: Add the source operand to the destination operand and store the

result in the destination location.

Condition codes: X N Z V C

* * * * *

Source operand addressing modes

Destination operand addressing modes

ADDA Add address

Operation: [destination] [source] + [destination]

Syntax: ADDA <ea>,An

Attributes: Size = word, longword

Description: Add the source operand to the destination address register and

store the result in the destination address register. The source is

sign-extended before it is added to the destination. For example,

if we execute where A4 = 00000100 and D3.W =

ADDA.W D3,A4 16

8002 , the contents of D3 are sign-extended to FFFF8002 and

16 16

added to 00000100 to give FFFF8102 , which is stored in A4.

16 16

The 68000's Instruction Set

4 Application: To add to the contents of an address register and not update the

CCR. Note that is the same as .

ADDA.W D0,A0 LEA (A0,D0.W),A0

Condition codes: X N Z V C

- - - - -

An operation does not affect the state of the CCR.

ADDA

Source operand addressing modes

ADDI Add immediate

Operation: [destination] <literal> + [destination]

Syntax: ADDI #<data>,<ea>

Attributes: Size = byte, word, longword

Description: Add immediate data to the destination operand. Store the result

in the destination operand. can be used to add a literal

ADDI

directly to a memory location. For example, ADDI.W #$1234,$2000

has the effect [M(2000 )] [M(2000 )] + 1234 .

16 16 16

Condition codes: X N Z V C

* * * * *

Destination operand addressing modes

ADDQ Add quick ←

Operation: [destination] <literal> + [destination]

Syntax: ADDQ #<data>,<ea>

The 68000's Instruction Set 5

Sample syntax: ADDQ #6,D3

Attributes: Size = byte, word, longword

Description: Add the immediate data to the contents of the destination operand.

The immediate data must be in the range 1 to 8. Word and

longword operations on address registers do not affect condition

codes. Note that a word operation on an address register affects

all bits of the register.

Application: is used to add a small constant to the operand at the effective

ADDQ

address. Some assemblers permit you to write and then choose

ADD

automatically if the constant is in the range 1 to 8.

ADDQ

Condition codes: Z N Z V C

* * * * *

Note that the CCR is not updated if the destination operand is an

address register.

Destination operand addressing modes

ADDX Add extended

Operation: [destination] [source] + [destination] + [X]

Syntax: ADDX Dy,Dx

ADDX -(Ay),-(Ax)

Attributes: Size = byte, word, longword

Description: Add the source operand to the destination operand along with

the extend bit, and store the result in the destination location.

The only legal addressing modes are data register direct and

memory to memory with address register indirect using pre-

decrementing.

Application: The instruction is used in chain arithmetic to add together

ADDX

strings of bytes (words or longwords). Consider the addition of

The 68000's Instruction Set

6 two 128-bit numbers, each of which is stored as four consecutive

longwords.

LEA Number1,A0 A0 points at first number

LEA Number2,A1 A1 points at second number

MOVE #3,D0 Four longwords to add

MOVE #$00,CCR Clear X-bit and Z-bit of the CCR

LOOP ADDX -(A0),-(A1) Add pair of numbers

DBRA D0,LOOP Repeat until all added

Condition codes: X N Z V C

* * * * *

The Z-bit is cleared if the result is non-zero, and left unchanged

otherwise. The Z-bit can be used to test for zero after a chain of

multiple precision operations.

AND AND logical

Operation: [destination] [source].[destination]

Syntax: AND <ea>,Dn

AND Dn,<ea>

Attributes: Size = byte, word, longword

Description: AND the source operand to the destination operand and store

the result in the destination location.

Application: is used to mask bits. If we wish to clear bits 3 to 6 of data

AND

register D7, we can execute . Unfortunately,

AND #%10000111,D7

the operation cannot be used with an address register as

AND

either a source or a destination operand. If you wish to perform a

logical operation on an address register, you have to copy the

address to a data register and then perform the operation there.

Condition codes: X N Z V C

- * * 0 0

Source operand addressing modes

The 68000's Instruction Set 7

Destination operand addressing modes

ANDI AND immediate

Operation: [destination] <literal>.[destination]

Syntax: ANDI #<data>,<ea>

Attributes: Size = byte, word, longword

Description: AND the immediate data to the destination operand. The ANDI

permits a literal operand to be ANDed with a destination other

than a data register. For example, or

ANDI #$FE00,$1234

.

ANDI.B #$F0,(A2)+

Condition codes: X N Z V C

- * * 0 0

Destination operand addressing modes

ANDI to CCR AND immediate to condition

code register

Operation: [CCR] <data>.[CCR]

Syntax: ANDI #<data>,CCR

Attributes: Size = byte

Description: AND the immediate data to the condition code register (i.e., the

least-significant byte of the status register).

The 68000's Instruction Set

8 Application: is used to clear selected bits of the CCR. For example,

ANDI clears the Z- and C-bits, i.e., XNZVC = X N 0 V 0.

ANDI #$FA,CCR

Condition codes: X N Z V C

* * * * *

X: cleared if bit 4 of data is zero

N: cleared if bit 3 of data is zero

Z: cleared if bit 2 of data is zero

V: cleared if bit 1 of data is zero

C: cleared if bit 0 of data is zero

ANDI to SR AND immediate to status register

Operation: =

IF [S] 1

THEN ←

[SR] <literal>.[SR]

ELSE TRAP

Syntax: ANDI #<data>,SR

Attributes: Size = word

Description: AND the immediate data to the status register and store the

result in the status register. All bits of the SR are affected.

Application: This instruction is used to clear the interrupt mask, the S-bit, and

the T-bit of the SR. affects both the status byte

ANDI #<data>,SR

of the SR and the CCR. For example, clears the

ANDI #$7FFF,SR

trace bit of the status register, while clears the

ANDI #$7FFE,SR

trace bit and also clears the carry bit of the CCR.

Condition codes: X N Z V C

* * * * *

ASL, ASR Arithmetic shift left/right

Operation: [destination] [destination] shifted by <count>

Syntax: ASL Dx,Dy

ASR Dx,Dy

ASL #<data>,Dy

ASR #<data>,Dy

ASL <ea>

ASR <ea>

The 68000's Instruction Set 9

Attributes: Size = byte, word, longword

Description: Arithmetically shift the bits of the operand in the specified direc-

tion (i.e., left or right). The shift count may be specified in one of

three ways. The count may be a literal, the contents of a data

register, or the value 1. An immediate (i.e., literal) count permits

a shift of 1 to 8 places. If the count is in a register, the value is

modulo 64 (i.e., 0 to 63). If no count is specified, one shift is made

(i.e., shifts the contents of the word at the effective

ASL <ea>

address one place left).

The effect of an arithmetic shift left is to shift a zero into the

least-significant bit position and to shift the most-significant bit

out into both the X- and the C-bits of the CCR. The overflow bit

of the CCR is set if a sign change occurs during shifting (i.e., if

the most-significant bit changes value during shifting).

The effect of an arithmetic shift right is to shift the least-

significant bit into both the X- and C-bits of the CCR. The most-

significant bit (i.e., the sign bit) is replicated to preserve the sign of

the number.

Application: multiplies a two’s complement number by 2. is almost

ASL ASL

identical to the corresponding logical shift, . The only differ-

LSR

ence between and is that sets the V-bit of the CCR if

ASL LSL ASL

overflow occurs, while clears the V-bit to zero. An divides

LSL ASR

a two’s complement number by 2. When applied to the contents

of a memory location, all 68000 shift operations operate on a word.

Condition codes: X N Z V C

* * * * *

The X-bit and the C-bit are set according to the last bit shifted out

of the operand. If the shift count is zero, the C-bit is cleared. The

V-bit is set if the most-significant bit is changed at any time

during the shift operation and cleared otherwise.

The 68000's Instruction Set

10 Destination operand addressing modes

Bcc Branch on condition cc

Operation: If cc = 1 THEN [PC] [PC] + d

Syntax: Bcc <label>

Sample syntax: BEQ Loop_4

BVC *+8

Attributes: takes an 8-bit or a 16-bit offset (i.e., displacement).

BEQ

Description: If the specified logical condition is met, program execution

continues at location [PC] + displacement, d. The displacement is

a two’s complement value. The value in the PC corresponds to

the current location plus two. The range of the branch is -126 to

+128 bytes with an 8-bit offset, and -32K to +32K bytes with a 16-

bit offset. A short branch to the next instruction is impossible,

since the branch code 0 indicates a long branch with a 16-bit

offset. The assembly language form means branch to the

BCC *+8

point eight bytes from the current PC if the carry bit is clear.

branch on carry clear C

BCC branch on carry set C

BCS branch on equal Z

BEQ branch on greater than or equal N.V + N.V

BGE branch on greater than N.V.Z + N.V.Z

BGT branch on higher than C.Z

BHI branch on less than or equal Z + N.V + N.V

BLE branch on lower than or same C + Z

BLS branch on less than N.V + N.V

BLT branch on minus (i.e., negative) N

BMI branch on not equal Z

BNE branch on plus (i.e., positive) N

BPL branch on overflow clear V

BVC branch on overflow set V

BVS

Note that there are two types of conditional branch instruction:

The 68000's Instruction Set 11

those that branch on an unsigned condition and those that branch

on a signed condition. For example, $FF is greater than $10 when

the numbers are regarded as unsigned (i.e., 255 is greater than

16). However, if the numbers are signed, $FF is less than $10 (i.e.,

-1 is less than 16).

The signed comparisons are:

branch on greater than or equal

BGE branch on greater than

BGT branch on lower than or equal

BLE branch on less than

BLT

The unsigned comparisons are:

branch on higher than or same

BHS BCC branch on higher than

BHI branch on lower than or same

BLS branch on less than

BLO BCS

The official mnemonics (branch on carry clear) and (branch

BCC BCS

on carry set) can be renamed as (branch on higher than or

BHS

same) and (branch on less than), respectively. Many 68000

BLO

assemblers support these alternative mnemonics.

Condition codes: X N Z V C

- - - - -

BCHG Test a bit and change

Operation: [Z] <bit number> OF [destination]

<bit number> OF [destination] <bit number> OF [destination]

Syntax: BCHG Dn,<ea>

BCHG #<data>,<ea>

Attributes: Size = byte, longword

Description: A bit in the destination operand is tested and the state of the

specified bit is reflected in the condition of the Z-bit in the CCR.

After the test operation, the state of the specified bit is changed

in the destination. If a data register is the destination, then the bit

numbering is modulo 32, allowing bit manipulation of all bits in

a data register. If a memory location is the destination, a byte is

The 68000's Instruction Set

12 read from that location, the bit operation performed using the bit

number modulo 8, and the byte written back to the location.

Note that bit zero refers to the least-significant bit. The bit number

for this operation may be specified either statically by an

immediate value or dynamically by the contents of a data register.

Application: If the operation is carried out and the contents of

BCHG #4,$1234

memory location $1234 are 10101010 , bit 4 is tested. It is a 0 and

2

therefore the Z-bit of the CCR is set to 1. Bit 4 of the destination

operand is changed and the new contents of location 1234 are

16

10111010 .

2

Condition codes: X N Z V C

- - * - -

Z: set if the bit tested is zero, cleared otherwise.

Destination operand addressing modes

Note that data register direct (i.e., Dn) addressing uses a longword

operand, while all other modes use a byte operand.

BCLR Test a bit and clear

Operation: [Z] <bit number> OF [destination]

<bit number> OF [destination] 0

Syntax: BCLR Dn,<ea>

BCLR #<data>,<ea>

Attributes: Size = byte, longword

Description: A bit in the destination operand is tested and the state of the

specified bit is reflected in the condition of the Z-bit in the

condition code. After the test, the state of the specified bit is

cleared in the destination. If a data register is the destination, the

bit numbering is modulo 32, allowing bit manipulation of all bits

in a data register. If a memory location is the destination, a byte

is read from that location, the bit operation performed using the

bit number modulo 8, and the byte written back to the location.

The 68000's Instruction Set 13

Bit zero refers to the least-significant bit. The bit number for this

operation may be specified either by an immediate value or

dynamically by the contents of a data register.

Application: If the operation is carried out and the contents of

BCLR #4,$1234

memory location $1234 are 11111010 , bit 4 is tested. It is a 1 and

2

therefore the Z-bit of the CCR is set to 0. Bit 4 of the destination

operand is cleared and the new contents of $1234 are: 11101010 .

2

Condition codes: X N Z V C

- - * - -

Z: set if the bit tested is zero, cleared otherwise.

Destination operand addressing modes

Note that data register direct (i.e., Dn) addressing uses a longword

operand, while all other modes use a byte operand.

BRA Branch always

Operation: [PC] [PC] + d

Syntax: BRA <label>

BRA <literal>

Attributes: Size = byte, word

Description: Program execution continues at location [PC] + d. The displace-

ment, d, is a two’s complement value (8 bits for a short branch

and 16 bits for a long branch). The value in the PC corresponds

to the current location plus two. Note that a short branch to the

next instruction is impossible, since the branch code 0 is used to

indicate a long branch with a 16-bit offset.

Application: A is an unconditional relative jump (or goto). You use a

BRA BRA

instruction to write position independent code, because the

destination address (branch target address) is specified with respect

to the current value of the PC. A instruction does not produce

JMP

position independent code.

The 68000's Instruction Set

14 Condition codes: X N Z V C

- - - - -

BSET Test a bit and set

Operation: [Z] <bit number> OF [destination]

<bit number> OF [destination] 1

Syntax: BSET Dn,<ea>

BSET #<data>,<ea>

Attributes: Size = byte, longword

Description: A bit in the destination operand is tested and the state of the

specified bit is reflected in the condition of the Z-bit of the

condition code. After the test, the specified bit is set in the

destination. If a data register is the destination then the bit

numbering is modulo 32, allowing bit manipulation of all bits in

a data register. If a memory location is the destination, a byte is

read from that location, the bit operation performed using bit

number modulo 8, and the byte written back to the location. Bit

zero refers to the least-significant bit. The bit number for this

operation may be specified either by an immediate value or

dynamically by the contents of a data register.

Condition codes: X N Z V C

- - * - -

Z: set if the bit tested is zero, cleared otherwise.

Destination operand addressing mode for form

BSET Dn,<ea>

Note that data register direct (i.e., Dn) addressing uses a longword

operand, while all other modes use a byte operand.

BSR Branch to subroutine

← ← ←

Operation: [SP] [SP] - 4; [M([SP])] [PC]; [PC] [PC] + d

The 68000's Instruction Set 15

Syntax: BSR <label>

BSR <literal>

Attributes: Size = byte, word

Description: The longword address of the instruction immediately following

the instruction is pushed onto the system stack pointed at by

BSR

A7. Program execution then continues at location [PC] +

displacement. The displacement is an 8-bit two’s complement

value for a short branch, or a 16-bit two’s complement value for

a long branch. The value in the PC corresponds to the current

location plus two. Note that a short branch to the next instruction

is impossible, since the branch code 0 is used to indicate a long

branch with a 16-bit offset.

Application: is used to call a procedure or a subroutine. Since it provides

BSR

relative addressing (and therefore position independent code),

its use is preferable to .

JSR

Condition codes: X N Z V C

- - - - -

BTST Test a bit

Operation: [Z] <bit number> OF [destination]

Syntax: BTST Dn,<ea>

BTST #<data>,<ea>

Attributes: Size = byte, longword

Description: A bit in the destination operand is tested and the state of the

specified bit is reflected in the condition of the Z-bit in the CCR.

The destination is not modified by a instruction. If a data

BTST

register is the destination, then the bit numbering is modulo 32,

allowing bit manipulation of all bits in a data register. If a memory

location is the destination, a byte is read from that location, the

bit operation performed. Bit 0 refers to the least-significant bit.

The bit number for this operation may be specified either statically

by an immediate value or dynamically by the contents of a data

register.

Condition codes: X N Z V C

- - * - -

Z: set if the bit tested is zero, cleared otherwise.

The 68000's Instruction Set

16 Destination operand addressing modes for form

BTST Dn,<ea>

Note that data register direct (i.e., Dn) addressing uses a longword

operand, while all other modes use a byte operand.

CHK Check register against bounds

Operation: IF [Dn] < 0 OR [Dn] > [<ea>] THEN TRAP

Syntax: CHK <ea>,Dn

Attributes: Size = word

Description: The contents of the low-order word in the data register specified

in the instruction are examined and compared with the upper

bound at the effective address. The upper bound is a two’s

complement integer. If the data register value is less than zero or

greater than the upper bound contained in the operand word,

then the processor initiates exception processing.

Application: The instruction can be used to test the bounds of an array

CHK

element before it is used. By performing this test, you can make

certain that you do not access an element outside an array.

Consider the following fragment of code:

MOVE.W subscript,D0 Get subscript to test

CHK #max_bound,D0 Test subscript against 0 and upper bound

* TRAP on error ELSE continue if ok

Condition codes: X N Z V C

- * U U U

N: set if ; cleared if ; undefined otherwise.

[Dn] < 0 [Dn] > [<ea>]

Source operand addressing modes

The 68000's Instruction Set 17

CLR Clear an operand

Operation: [destination] 0

Syntax: CLR <ea>

Sample syntax: CLR (A4)+

Attributes: Size = byte, word, longword

Description: The destination is cleared — loaded with all zeros. The in-

CLR

struction can't be used to clear an address register. You can use

to clear A0. Note that a side effect of ’s imple-

SUBA.L A0,A0 CLR

mentation is a read from the specified effective address before the

clear (i.e., write) operation is executed. Under certain circum-

stances this might cause a problem (e.g., with write-only memory).

Condition codes: X N Z V C

- 0 1 0 0

Source operand addressing modes

CMP Compare

Operation: [destination] - [source]

Syntax: CMP <ea>,Dn

Sample syntax: CMP (Test,A6,D3.W),D2

Attributes: Size = byte, word, longword

Description: Subtract the source operand from the destination operand and

set the condition codes accordingly. The destination must be a

data register. The destination is not modified by this instruction.

Condition codes: X N Z V C

- * * * *

The 68000's Instruction Set

18 Source operand addressing modes

CMPA Compare address

Operation: [destination] - [source]

Syntax: CMPA <ea>,An

Sample syntax: CMPA.L #$1000,A4

CMPA.W (A2)+,A6

CMPA.L D5,A2

Attributes: Size = word, longword

Description: Subtract the source operand from the destination address register

and set the condition codes accordingly. The address register is

not modified. The size of the operation may be specified as word

or longword. Word length operands are sign-extended to 32 bits

before the comparison is carried out.

Condition codes: X N Z V C

- * * * *

Source operand addressing modes

CMPI Compare immediate

Operation: [destination] - <immediate data>

Syntax: CMPI #<data>,<ea>

Attributes: Size = byte, word, longword

The 68000's Instruction Set 19

Description: Subtract the immediate data from the destination operand and

set the condition codes accordingly — the destination is not

modified. permits the comparison of a literal with memory.

CMPI

Condition codes: X N Z V C

- * * * *

Destination operand addressing modes

CMPM Compare memory with memory

Operation: [destination] - [source]

Syntax: CMPM (Ay)+,(Ax)+

Attributes: Size = byte, word, longword

Sample syntax: CMPM.B (A3)+,(A4)+

Description: Subtract the source operand from the destination operand and

set the condition codes accordingly. The destination is not

modified by this instruction. The only permitted addressing mode

is address register indirect with post-incrementing for both source

and destination operands.

Application: Used to compare the contents of two blocks of memory. For

example:

* Compare two blocks of memory for equality

LEA Source,A0 A0 points to source block

LEA Destination,A1 A1 points to destination block

MOVE.W #Count-1,D0 Compare Count words

RPT CMPM.W (A0)+,(A1)+ Compare pair of words

DBNE D0,RPT Repeat until all done

.

.

Condition codes: X N Z V C

- * * * *

The 68000's Instruction Set

20 DBcc Test condition, decrement, and branch

Operation: IF(condition false)

THEN [Dn] [Dn] - 1 {decrement loop counter}

= ←

IF [Dn] -1 THEN [PC] [PC] + 2 {fall through to next instruction}

ELSE [PC] [PC] + d {take branch}

ELSE [PC] [PC] + 2 {fall through to next instruction}

Syntax: DBcc Dn,<label>

Attributes: Size = word

Description: The instruction provides an automatic looping facility and

DBcc

replaces the usual decrement counter, test, and branch instruc-

tions. Three parameters are required by the instruction: a

DBcc

branch condition (specified by ‘cc’), a data register that serves as

the loop down-counter, and a label that indicates the start of the

loop. The first tests the condition ‘cc’, and if ‘cc’ is true the

DBcc

loop is terminated and the branch back to not taken.

<label>

The 14 branch conditions supported by are also supported

Bcc

by , as well as and (F = false, and T = true). Note

DBcc DBF DBT

that many assemblers permit the mnemonic to be expressed

DBF

as (i.e., decrement and branch back).

DBRA

It is important to appreciate that the condition tested by the DBcc

instruction works in the opposite sense to a , conditional branch,

Bcc

instruction. For example, means branch on carry clear,

BCC

whereas means continue (i.e., exit the loop) on carry clear.

DBCC

That is, the condition is a loop terminator. If the termination

DBcc

condition is not true, the low-order 16 bits of the specified data

register are decremented. If the result is -1, the loop is not taken

and the next instruction is executed. If the result is not -1, a

branch is made to ‘label’. Note that the label represents a 16-bit

signed value, permitting a branch range of -32K to +32K bytes.

Since the value in Dn decremented is 16 bits, the loop may be

executed up to 64K times.

We can use the instruction , decrement and branch on zero,

DBEQ

to mechanize the high-level language construct .

REPEAT...UNTIL

LOOP ... REPEAT

...

... [D0] := [D0] - 1

...

DBEQ D0,REPEAT UNTIL [D0] = - 1 OR [Z] = 1

The 68000's Instruction Set 21

Application: Suppose we wish to input a block of 512 bytes of data (the data is

returned in register D1). If the input routine returns a value zero

in D1, an error has occurred and the loop must be exited.

LEA Dest,A0 Set up pointer to destination

MOVE.W #511,D0 512 bytes to be input

AGAIN BSR INPUT Get the data in D1

MOVE.B D1,(A0)+ Store it

DBEQ D0,AGAIN REPEAT until D1 = 0 OR 512 times

Condition codes: X N Z V C

- - - - -

Not affected

DIVS, DIVU Signed divide, unsigned divide

Operation: [destination] [destination]/[source]

Syntax: DIVS <ea>,Dn

DIVU <ea>,Dn

Attributes: Size = longword/word = longword result

Description: Divide the destination operand by the source operand and store

the result in the destination. The destination is a longword and

the source is a 16-bit value. The result (i.e., destination register) is

a 32-bit value arranged so that the quotient is the lower-order

word and the remainder is the upper-order word. performs

DIVU

division on unsigned values, and performs division on two’s

DIVS

complement values. An attempt to divide by zero causes an

exception. For , the sign of the remainder is always the same

DIVS

as the sign of the dividend (unless the remainder is zero).

Attempting to divide a number by zero results in a divide-by-zero

exception. If overflow is detected during division, the operands

are unaffected. Overflow is checked for at the start of the opera-

tion and occurs if the quotient is larger than a 16-bit signed inte-

ger. If the upper word of the dividend is greater than or equal to

the divisor, the V-bit is set and the instruction terminated.

Application: Consider the division of D0 by D1, , which results in:

DIVU D1,D0

[D0(0:15)] [D0(0:31)]/[D1(0:15)]

[D0(16:31)] remainder

The 68000's Instruction Set

22 Condition codes: X N Z V C

- * * * 0

The X-bit is not affected by a division. The N-bit is set if the

quotient is negative. The Z-bit is set if the quotient is zero. The V-

bit is set if division overflow occurs (in which case the Z- and N-

bits are undefined). The C-bit is always cleared.

Source operand addressing modes

EOR Exclusive OR logical

← ⊕

Operation: [destination] [source] [destination]

Syntax: EOR Dn,<ea>

Sample syntax: EOR D3,-(A3)

Attributes: Size = byte, word, longword.

Description: EOR (exclusive or) the source operand with the destination

operand and store the result in the destination location. Note that

the source operand must be a data register and that the operation

is not permitted.

EOR <ea>,Dn

Application: The EOR instruction is used to toggle (i.e., change the state of)

selected bits in the operand. For example, if [D0] = 00001111, and

[D1] = 10101010, the operation toggles bits 0 to 3 of

EOR.B D0,D1

D1 and results in [D1] = 10100101.

Condition codes: X N Z V C

- * * 0 0

Destination operand addressing modes

The 68000's Instruction Set 23

EORI EOR immediate

← ⊕

Operation: [destination] <literal> [destination]

Syntax: EORI #<data>,<ea>

Attributes: Size = byte, word, longword

Description: EOR the immediate data with the contents of the destination

operand. Store the result in the destination operand.

Condition codes: X N Z V C

- * * 0 0

Destination operand addressing modes

EORI to CCR EOR immediate to CCR

← ⊕

Operation: [CCR] <literal> [CCR]

Syntax: EORI #<data>,CCR

Attributes: Size = byte

Description: EOR the immediate data with the contents of the condition code

register (i.e., the least-significant byte of the status register).

Application: Used to toggle bits in the CCR. For example, EORI #$0C,CCR

toggles the N- and Z-bits of the CCR.

Condition codes: X N Z V C

* * * * *

X:= toggled if bit 4 of data = 1; unchanged otherwise

N:= toggled if bit 3 of data = 1; unchanged otherwise

Z:= toggled if bit 2 of data = 1; unchanged otherwise

V:= toggled if bit 1 of data = 1; unchanged otherwise

C:= toggled if bit 0 of data = 1; unchanged otherwise

The 68000's Instruction Set

24 EORI to SR EOR immediate to status register

Operation: IF [S] = 1

THEN ← ⊕

[SR] <literal> [SR]

ELSE TRAP

Syntax: EORI #<data>,SR

Attributes: Size = word

Description: EOR (exclusive OR) the immediate data with the contents of the

status register and store the result in the status register. All bits

of the status register are affected.

Condition codes: X N Z V C

* * * * *

X:= toggled if bit 4 of data = 1; unchanged otherwise

N:= toggled if bit 3 of data = 1; unchanged otherwise

Z:= toggled if bit 2 of data = 1; unchanged otherwise

V:= toggled if bit 1 of data = 1; unchanged otherwise

C:= toggled if bit 0 of data = 1; unchanged otherwise

EXG Exchange registers

← ←

Operation: [Rx] [Ry]; [Ry] [Rx]

Syntax: EXG Rx,Ry

Sample syntax: EXG D3,D4

EXG D2,A0

EXG A7,D5

Attributes: Size = longword

Description: Exchange the contents of two registers. The size of the instruction

is a longword because the entire 32-bit contents of two registers

are exchanged. The instruction permits the exchange of address

registers, data registers, and address and data registers.

Application: One application of is to load an address into a data register

EXG

and then process it using instructions that act on data registers.

Then the reverse operation can be used to return the result to the

The 68000's Instruction Set 25

address register. Doing this preserves the original contents of the

data register.

Condition codes: X N Z V C

- - - - -

EXT Sign-extend a data register

Operation: [destination] sign-extended[destination]

Syntax: EXT.W Dn

EXT.L Dn

Attributes: Size = word, longword

Description: Extend the least-significant byte in a data register to a word, or

extend the least-significant word in a data register to a longword.

If the operation is word sized, bit 7 of the designated data register

is copied to bits (8:15). If the operation is longword sized, bit 15

is copied to bits (16:31).

Application: If results in 12340078

[D0] = $12345678, EXT.W D0 16

If results in 00005678

[D0] = $12345678, EXT.L D0 16

Condition codes: X N Z V C

- * * 0 0

ILLEGAL Illegal instruction

← ←

Operation: [SSP] [SSP] - 4; [M([SSP])] [PC];

← ←

[SSP] [SSP] - 2; [M([SSP])] [SR];

[PC] Illegal instruction vector

Syntax: ILLEGAL

Attributes: None

Description: The bit pattern of the illegal instruction, 4AFC causes the illegal

16

instruction trap to be taken. As in all exceptions, the contents of

the program counter and the processor status word are pushed

onto the supervisor stack at the start of exception processing.

The 68000's Instruction Set

26 Application: Any unknown pattern of bits read by the 68000 during an instruc-

tion read phase will cause an illegal instruction trap. The ILLEGAL

instruction can be thought of as an official illegal instruction. It

can be used to test the illegal instruction trap and will always be

an illegal instruction in any future enhancement of the 68000.

Condition codes: X N Z V C

- - - - -

JMP Jump (unconditionally)

Operation: [PC] destination

Syntax: JMP <ea>

Attributes: Unsized

Description: Program execution continues at the effective address specified by

the instruction.

Application: Apart from a simple unconditional jump to an address fixed at

compile time (i.e., ), the instruction is useful for

JMP label JMP

the calculation of dynamic or computed jumps. For example, the

instruction jumps to the location pointed at by

JMP (A0,D0.L)

the contents of address register A0, offset by the contents of data

register D0. Note that provides several addressing modes,

JMP

while provides a single addressing mode (i.e., PC relative).

BRA

Condition codes: X N Z V C

- - - - -

Source operand addressing modes

JSR Jump to subroutine

← ←

Operation: [SP] [SP] - 4; [M([SP])] [PC]

[PC] destination

The 68000's Instruction Set 27

Syntax: JSR <ea>

Attributes: Unsized

Description: pushes the longword address of the instruction immediately

JSR

following the onto the system stack. Program execution then

JSR

continues at the address specified in the instruction.

Application: calls the procedure pointed at by address register Ai.

JSR (Ai)

The instruction calls the procedure at the location

JSR (Ai,Dj)

[Ai] + [Dj] which permits dynamically computed addresses.

Condition codes: X N Z V C

- - - - -

Source operand addressing modes

LEA Load effective address

Operation: [An] <ea>

Syntax: LEA <ea>,An

Sample syntax: LEA Table,A0

LEA (Table,PC),A0

LEA (-6,A0,D0.L),A6

LEA (Table,PC,D0),A6

Attributes: Size = longword

Description: The effective address is computed and loaded into the specified

address register. For example, calculates

LEA (-6,A0,D0.W),A1

the sum of address register A0 plus data register D0.W sign-

extended to 32 bits minus 6, and deposits the result in address

register A1. The difference between the and instructions

LEA PEA

is that calculates an effective address and puts it in an ad-

LEA

dress register, while calculates an effective address in the

PEA

same way but pushes it on the stack.


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DETTAGLI
Corso di laurea: Corso di laurea in ingegneria informatica
SSD:
A.A.: 2013-2014

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher flaviael di informazioni apprese con la frequenza delle lezioni di Architetture Sistemi Elaborazione e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università Napoli Federico II - Unina o del prof Mazzocca Nicola.

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