Motorola 68000 - Instruction set

NEGtraction

All bits of the condition code register are modified by a NEG operation. For example, if D3.B = 11100111, the logical operation results in D3 = 00011001 (XNZVC=10001) and NEG.B D3 = 00011000 (XNZVC=-0000). NOT.B D3

Condition codes: X N Z V C* * * * *

Note that the X-bit is set to the value of the C-bit.

The 68000's Instruction Set 41

Destination operand addressing modes

NEGX Negate with extend

Operation: [destination] 0 - [destination] - [X]

Syntax: NEGX <ea>

Attributes: Size = byte, word, longword

Description: The operand addressed as the destination and the extend bit are subtracted from zero. NEGX is the same as NEG except that the X-bit is also subtracted from zero.

Condition codes: X N Z V C* * * * *

The Z-bit is cleared if the result is non-zero and is unchanged otherwise. The X-bit is set to the same value as the C-bit.

Destination operand addressing modes

NOP No operation

Operation: None

Syntax: NOP

Attributes: Unsized

Description: The no operation instruction.

The NOP instruction performs no computation. Execution continues with the instruction following the NOP instruction. The processor's state is not modified by a NOP.

The 68000's Instruction Set can be used to introduce a delay in code. Some programmers use them to provide space for patches - two or more NOPs can later be replaced by branch or jump instructions to fix a bug. This use of the NOP is seriously frowned upon, as errors should be corrected by re-assembling the code rather than by patching it.

Condition codes: X N Z V C

NOT Logical complement

Operation: [destination] = NOT [destination]

Syntax: NOT <ea>

Attributes: Size = byte, word, longword

Description: Calculate the logical complement of the destination and store the result in the destination. The difference between NOT and NEG is that NOT performs a bit-by-bit logical complementation, while NEG performs a two's complement arithmetic subtraction. Moreover, NOT updates all bits of the CCR, while NEG clears the V- and C-bits.

updates the N- and Z-bits, and doesn't affect the X-bit.

Condition codes: X N Z V C- * * 0 0

Source operand addressing modes

OR OR logical←

Operation: [destination] [source] + [destination]

Syntax: OR <ea>,Dn

OR Dn,<ea>

Attributes: Size = byte, word, longword

The 68000's Instruction Set 43

Description: OR the source operand to the destination operand, and store the result in the destination location.

Application: The instruction is used to set selected bits of the operand. For example, we can set the four most-significant bits of a longword operand in D0 by executing:

OR.L #$F0000000,D0

Condition codes: X N Z V C- * * 0 0

Source operand addressing modes

Destination operand addressing modes

ORI OR immediate←

Operation: [destination] <literal> + [destination]

Syntax: ORI #<data>,<ea>

Attributes: Size = byte, word, longword

Description: OR the immediate data with the destination operand. Store the result in the destination operand.

Condition codes: X N Z V C-

Application: forms the logical OR of the immediate source with the ORI effective address, which may be a memory location. For example, ORI.B #%00000011,(A0)+

The 68000's Instruction Set

Destination operand addressing modes

ORI to CCR

Inclusive OR immediate to CCR

Operation: [CCR] <literal> + [CCR]

Syntax: ORI #<data>,CCR

Attributes: Size = byte

Description: OR the immediate data with the condition code register (i.e., the least-significant byte of the status register). For example, the Z flag of the CCR can be set by .ORI #$04,CCR

Condition codes: X N Z V C

* * * * *

X is set if bit 4 of data = 1; unchanged otherwise

N is set if bit 3 of data = 1; unchanged otherwise

Z is set if bit 2 of data = 1; unchanged otherwise

V is set if bit 1 of data = 1; unchanged otherwise

C is set if bit 0 of data = 1; unchanged otherwise

ORI to SR

Inclusive OR immediate to status register

Operation: IF [S] = 1 THEN ←[SR] <literal> + [SR] ELSE TRAP

Syntax: ORI #<data>,SR

Attributes:

Size = word

Description: OR the immediate data to the status register and store the result in the status register. All bits of the status register are affected.

The 68000's Instruction Set 45

Application: Used to set bits in the SR (i.e., the S, T, and interrupt mask bits). For example, sets bit 15 of the SR (i.e., the trace ORI #$8000,SR bit).

Condition codes: X N Z V C

X is set if bit 4 of data = 1; unchanged otherwise

N is set if bit 3 of data = 1; unchanged otherwise

Z is set if bit 2 of data = 1; unchanged otherwise

V is set if bit 1 of data = 1; unchanged otherwise

C is set if bit 0 of data = 1; unchanged otherwise

PEA Push effective address

Operation: [SP] [SP] - 4; [M([SP])] <ea>

Syntax: PEA <ea>

Attributes: Size = longword

Description: The longword effective address specified by the instruction is computed and pushed onto the stack. The difference between PEA and LEA is that LEA calculates an effective address and puts it in an address register, while PEA pushes the effective address onto the stack.

calculates an effective address PEA in the same way but pushes it on the stack.

Application: calculates an effective address to be used later in address PEA register indirect addressing. In particular, it facilitates the writing of position independent code. For example, PEA (TABLE,PC) calculates the address of TABLE with respect to the PC and pushes it on the stack. This address can be read by a procedure and then used to access the data to which it points. Consider the example:

1. PEA Wednesday - Push the parameter address on the stack
2. BSR Subroutine - Call the procedure
3. LEA (4,SP),SP - Remove space occupied by the parameter
4. Subroutine MOVEA.L (4,SP),A0 - A0 points to parameter under return address
5. MOVE.W (A0),D2 - Access the actual parameter - Wednesday
6. RTS

Condition codes: X N Z V C - - - - -

The 68000's Instruction Set

46 Source operand addressing modes

RESET Reset external devices

Operation: IF [S] = 1 THEN Assert RESET* line ELSE TRAP

Syntax: RESET

Attributes: Unsized

Description: The reset line is asserted,

causing all external devices connected to the 68000's RESET* output to be reset. The instruction is RESET privileged and has no effect on the operation of the 68000 itself. This instruction is used to perform a programmed reset of all peripherals connected to the 68000's RESET* pin.

Condition codes: X N Z V C- - - - -

ROL, ROR Rotate left/right (without extend)

Operation: [destination] [destination] rotated by <count>

Syntax: ROL Dx,Dy
ROR Dx,Dy
ROL #<data>,Dy
ROR #<data>,Dy
ROL <ea>
ROR <ea>

Attributes: Size = byte, word, longword

Description: Rotate the bits of the operand in the direction indicated. The extend bit, X, is not included in the operation. A rotate operation is circular in the sense that the bit shifted out at one end is shifted into the other end. That is, no bit is lost or destroyed by a rotate operation. The bit shifted out is also copied into the C-bit of the CCR, but not into the X-bit. The shift count may be

The count can be specified in one of three ways: the count may be a literal, the contents of a data register, or the value 1. An immediate count permits a shift of 1 to 8 places. If the count is in a register, the value is modulo 64, allowing a range of 0 to 63. If no count is specified, the word at the effective address is rotated by one place (e.g., ROL <ea>).

ROL <ea>

Condition codes: X N Z V C- * * 0 *

The X-bit is not affected and the C-bit is set to the last bit rotated out of the operand (C is set to zero if the shift count is 0).

Destination operand addressing modes

ROXL, ROXR Rotate left/right with extend

Operation: [destination] [destination] rotated by <count>

Syntax: ROXL Dx,Dy
ROXR Dx,Dy
ROXL #<data>,Dy
ROXR #<data>,Dy
ROXL <ea>
ROXR <ea>

Attributes: Size = byte, word, longword

The 68000's Instruction Set48 Description: Rotate the bits of the operand in the direction indicated. The extend bit of the CCR is included in the rotation. A rotate operation is circular in the

sense that the bit shifted out at one end is shifted into the other end. That is, no bit is lost or destroyed by a rotate operation. Since the X-bit is included in the rotate, the rotation is performed over 9 bits (<B>), 17 bits (<W>), or 33 bits (<L>)..

The bit shifted out is also copied into the C-bit of the CCR as well as the X-bit. The shift count may be specified in one of three ways: the count may be a literal, the contents of a data register, or the value 1. An immediate count permits a shift of 1 to 8 places. If the count is in a register, the value is modulo 64 and the range is from 0 to 63. If no count is specified, the word at the specified effective address is rotated by one place (i.e., <ROXL> <ea>).

Condition codes: X N Z V C* * * 0 *

The X- and the C-bit are set to the last bit rotated out of the operand. If the rotate count is zero, the X-bit is unaffected and the C-bit is set to the X-bit.

Destination operand addressing modes

RTE Return from exception

Operation: IF [S] = 1 THEN

<code>
<p>← ←[SR] [M([SP])]; [SP] [SP] + 2← ←[PC] [M([SP])]; [SP] [SP] + 4</p>
<p>ELSE TRAP</p>
<p>The 68000's Instruction Set 49</p>
<p>Syntax: RTE</p>
<p>Attributes: Unsized</p>
<p>Description: The status register and program counter are pulled from the stack.
The previous values of the SR and PC are lost. The is used to
RTEterminate an exception handler. Note that the behavior of the
instruction depends on the nature of both the exception and
RTEprocessor type. The 68010 and later models push more informa-
tion on the stack following an exception than the 68000. The
processor determines how much to remove from the stack.</p>
<p>Condition codes: X N Z V C* * * * *</p>
<p>The CCR is restored to its pre-exception state.</p>
<p>RTR Return and restore condition codes</p>
<p>← ←Operation: [CCR] [M([SP])]; [SP] [SP] + 2← ←[PC] [M([SP])]; [SP] [SP] + 4</p>
<p>Syntax: RTR</p>
<p>Attributes: Unsized</p>
<p>Description: The condition code and program counter are pulled from the
stack. The previous condition code and program counter are lost.
The supervisor</p>
</code>

portion of the status register is not affected