Che materia stai cercando?

Motorola 68000 - Instruction set

Appunti in inglese di Architetture Sistemi Elaborazione del prof. Mazzocca su Motorola 68000 - Instruction set: ABCD (Add decimal with extend), ADD (Add binary), ADDA (Add address), ADDI (Add immediate), ADDQ (Add quick), ADDX (Add extended), AND logical, ASL, ASR (Arithmetic shift left/right)

Esame di Architetture Sistemi Elaborazione docente Prof. N. Mazzocca

Anteprima

ESTRATTO DOCUMENTO

The 68000's Instruction Set 25

address register. Doing this preserves the original contents of the

data register.

Condition codes: X N Z V C

- - - - -

EXT Sign-extend a data register

Operation: [destination] sign-extended[destination]

Syntax: EXT.W Dn

EXT.L Dn

Attributes: Size = word, longword

Description: Extend the least-significant byte in a data register to a word, or

extend the least-significant word in a data register to a longword.

If the operation is word sized, bit 7 of the designated data register

is copied to bits (8:15). If the operation is longword sized, bit 15

is copied to bits (16:31).

Application: If results in 12340078

[D0] = $12345678, EXT.W D0 16

If results in 00005678

[D0] = $12345678, EXT.L D0 16

Condition codes: X N Z V C

- * * 0 0

ILLEGAL Illegal instruction

← ←

Operation: [SSP] [SSP] - 4; [M([SSP])] [PC];

← ←

[SSP] [SSP] - 2; [M([SSP])] [SR];

[PC] Illegal instruction vector

Syntax: ILLEGAL

Attributes: None

Description: The bit pattern of the illegal instruction, 4AFC causes the illegal

16

instruction trap to be taken. As in all exceptions, the contents of

the program counter and the processor status word are pushed

onto the supervisor stack at the start of exception processing.

The 68000's Instruction Set

26 Application: Any unknown pattern of bits read by the 68000 during an instruc-

tion read phase will cause an illegal instruction trap. The ILLEGAL

instruction can be thought of as an official illegal instruction. It

can be used to test the illegal instruction trap and will always be

an illegal instruction in any future enhancement of the 68000.

Condition codes: X N Z V C

- - - - -

JMP Jump (unconditionally)

Operation: [PC] destination

Syntax: JMP <ea>

Attributes: Unsized

Description: Program execution continues at the effective address specified by

the instruction.

Application: Apart from a simple unconditional jump to an address fixed at

compile time (i.e., ), the instruction is useful for

JMP label JMP

the calculation of dynamic or computed jumps. For example, the

instruction jumps to the location pointed at by

JMP (A0,D0.L)

the contents of address register A0, offset by the contents of data

register D0. Note that provides several addressing modes,

JMP

while provides a single addressing mode (i.e., PC relative).

BRA

Condition codes: X N Z V C

- - - - -

Source operand addressing modes

JSR Jump to subroutine

← ←

Operation: [SP] [SP] - 4; [M([SP])] [PC]

[PC] destination

The 68000's Instruction Set 27

Syntax: JSR <ea>

Attributes: Unsized

Description: pushes the longword address of the instruction immediately

JSR

following the onto the system stack. Program execution then

JSR

continues at the address specified in the instruction.

Application: calls the procedure pointed at by address register Ai.

JSR (Ai)

The instruction calls the procedure at the location

JSR (Ai,Dj)

[Ai] + [Dj] which permits dynamically computed addresses.

Condition codes: X N Z V C

- - - - -

Source operand addressing modes

LEA Load effective address

Operation: [An] <ea>

Syntax: LEA <ea>,An

Sample syntax: LEA Table,A0

LEA (Table,PC),A0

LEA (-6,A0,D0.L),A6

LEA (Table,PC,D0),A6

Attributes: Size = longword

Description: The effective address is computed and loaded into the specified

address register. For example, calculates

LEA (-6,A0,D0.W),A1

the sum of address register A0 plus data register D0.W sign-

extended to 32 bits minus 6, and deposits the result in address

register A1. The difference between the and instructions

LEA PEA

is that calculates an effective address and puts it in an ad-

LEA

dress register, while calculates an effective address in the

PEA

same way but pushes it on the stack.

The 68000's Instruction Set

28 Application: is a very powerful instruction used to calculate an effective

LEA

address. In particular, the use of facilitates the writing of

LEA

position independent code. For example, LEA (TABLE,PC),A0

calculates the effective address of ‘ ’ with respect to the PC

TABLE

and deposits it in A0.

LEA (Table,PC),A0 Compute address of Table with respect to PC

MOVE (A0),D1 Pick up the first item in the table

. Do something with this item

MOVE D1,(A0) Put it back in the table

.

.

Table DS.B 100

Source operand addressing modes

Condition codes: X N Z V C

- - - - -

LINK Link and allocate

← ←

Operation: [SP] [SP] - 4; [M([SP])] [An];

← ←

[An] [SP]; [SP] [SP] + d

Syntax: LINK An,#<displacement>

Sample syntax: LINK A6,#-12

Attributes: Size = word

Description: The contents of the specified address register are first pushed

onto the stack. Then, the address register is loaded with the

updated stack pointer. Finally, the 16-bit sign-extended

displacement is added to the stack pointer. The contents of the

address register occupy two words on the stack. A negative

displacement must be used to allocate stack area to a procedure.

At the end of a instruction, the old value of address register

LINK

An has been pushed on the stack and the new An is pointing at

The 68000's Instruction Set 29

the base of the stack frame. The stack pointer itself has been

moved up by d bytes and is pointing at the top of the stack

frame. Address register An is called the frame pointer because it is

used to reference data on the stack frame. By convention,

programmers often use A6 as a frame pointer.

Application: The and pair are used to create local workspace on the

LINK UNLK

top of a procedure’s stack. Consider the code:

Subrtn LINK A6,#-12 Create a 12-byte workspace

.

MOVE D3,(-8,A6) Access the stack frame via A6

.

.

UNLK A6 Collapse the workspace

RTS Return from subroutine

Condition codes: X N Z V C

- - - - -

The instruction does not affect the CCR.

LINK

LSL, LSR Logical shift left/right

Operation: [destination] [destination] shifted by <count>

Syntax: LSL Dx,Dy

LSR Dx,Dy

LSL #<data>,Dy

LSR #<data>,Dy

LSL <ea>

LSR <ea>

Attributes: Size = byte, word, longword

Description: Logically shift the bits of the operand in the specified direction

(i.e., left or right). A zero is shifted into the input position and the

bit shifted out is copied into both the C- and the X-bit of the CCR.

The shift count may be specified in one of three ways. The count

may be a literal, the contents of a data register, or the value 1. An

immediate count permits a shift of 1 to 8 places. If the count is in

a register, the value is modulo 64 — from 0 to 63. If no count is

specified, one shift is made (e.g., shifts the word at the

LSL <ea>

effective address one position left).

The 68000's Instruction Set

30 Application: If [D3.W] = 1100110010101110 , the instruction LSL.W #5,D3

2

produces the result 1001010111000000 . After the shift, both the

2

X-and C-bits of the CCR are set to 1 (since the last bit shifted out

was a 1).

Condition codes: X N Z V C

* * * 0 *

The X-bit is set to the last bit shifted out of the operand and is

equal to the C-bit. However, a zero shift count leaves the X-bit

unaffected and the C-bit cleared.

Destination operand addressing modes

MOVE Copy data from source to destination

Operation: [destination] [source]

Syntax: MOVE <ea>,<e>

Sample syntax: MOVE (A5),-(A2)

MOVE -(A5),(A2)+

MOVE #$123,(A6)+

MOVE Temp1,Temp2

The 68000's Instruction Set 31

Attributes: Size = byte, word, longword

Description: Move the contents of the source to the destination location. The

data is examined as it is moved and the condition codes set

accordingly. Note that this is actually a copy command because

the source is not affected by the move. The move instruction has

the widest range of addressing modes of all the 68000’s

instructions.

Condition codes: X N Z V C

- * * 0 0

Source operand addressing modes

Destination operand addressing modes

MOVEA Move address

Operation: [An] [source]

Syntax: MOVEA <ea>,An

Attributes: Size = word, longword

Description: Move the contents of the source to the destination location. The

destination is an address register. The source must be a word or

longword. If it is a word, it is sign-extended to a longword. The

condition codes are not affected.

Application: The instruction is used to load an address register (some

MOVEA

assemblers simply employ the mnemonic for both and

MOVE MOVE

). Note that the instruction can often be used to perform

MOVEA LEA

the same operation (e.g., is the same as

MOVEA.L #$1234,A0

).

LEA $1234,A0

The 68000's Instruction Set

32 Take care because the instruction sign-extends

MOVEA.W #$8000,A0

the source operand to $FFFF8000 before loading it into A0,

whereas loads A0 with $00008000.

LEA $8000,A0

You should appreciate that the and instructions are

MOVEA LEA

not interchangeable. The operation cannot be

MOVEA (Ai),An

implemented by an instruction, since performs

LEA MOVEA (Ai),An

a memory access to obtain the source operand, as the following

RTL demonstrates. ←

=

LEA (Ai),An [An] [Ai]

=

MOVEA (Ai),An [An] [M([Ai])]

Condition codes: X N Z V C

- - - - -

Source operand addressing modes

MOVE to CCR Copy data to CCR from source

Operation: [CCR] [source]

Syntax: MOVE <ea>,CCR

Attributes: Size = word

Description: Move the contents of the source operand to the condition code

register. The source operand is a word, but only the low-order

byte contains the condition codes. The upper byte is neglected.

Note that is a word operation, but , , and

MOVE <ea>,CCR ANDI ORI

are all byte operations.

EORI to CCR

Application: The move to CCR instruction permits the programmer to preset

the CCR. For example, clears all the CCR’s bits.

MOVE #0,CCR

Condition codes: X N Z V C

* * * * *

The 68000's Instruction Set 33

Source operand addressing modes

MOVE from SR Copy data from SR to

destination

Operation: [destination] [SR]

Syntax: MOVE SR,<ea>

Attributes: Size = word

Description: Move the contents of the status register to the destination location.

The source operand, the status register, is a word. This instruction

is not privileged in the 68000, but is privileged in the 68010, 68020,

and 68030. Executing a while in the user mode on

MOVE SR,<ea>

these processors results in a privilege violation trap.

Condition codes: X N Z V C

- - - - -

Destination operand addressing modes

MOVE to SR Copy data to SR from source

Operation: IF [S] = 1 ←

THEN [SR] [source]

ELSE TRAP

Syntax: MOVE <ea>,SR

Attributes: Size = word

The 68000's Instruction Set

34 Description: Move the contents of the source operand to the status register.

The source operand is a word and all bits of the status register

are affected.

Application: The instruction allows the programmer to preset the

MOVE to SR

contents of the status register. This instruction permits the trace

mode, interrupt mask, and status bits to be modified. For example,

moves 00100111 00000000 to the status register

MOVE #$2700,SR

which clears all bits of the CCR, sets the S-bit, clears the T-bit,

and sets the interrupt mask level to 7.

Condition codes: X N Z V C

* * * * *

Source operand addressing modes

MOVE USP Copy data to or from USP

Operation 1: IF [S] = 1 {MOVE USP,An form}

THEN [USP] [An]

ELSE TRAP

Operation 2: IF [S] = 1 {MOVE An,USP form}

THEN [An] [USP]

ELSE TRAP

Syntax 1: MOVE USP,An

Syntax 2: MOVE An,USP

Attributes: Size = longword

Description: Move the contents of the user stack pointer to an address register

or vice versa. This is a privileged instruction and allows the

operating system running in the supervisor state either to read

the contents of the user stack pointer or to set up the user stack

pointer.

Condition codes: X N Z V C

- - - - -

The 68000's Instruction Set 35

MOVEM Move multiple registers

Operation 1 : REPEAT ←

[destination_register] [source]

UNTIL all registers in list moved

Operation 2: REPEAT ←

[destination] [source_register]

UNTIL all registers in list moved

Syntax 1: MOVEM <ea>,<register list>

Syntax 2: MOVEM <register list>,<ea>

Sample syntax: MOVEM.L D0-D7/A0-A6,$1234

MOVEM.L (A5),D0-D2/D5-D7/A0-A3/A6

MOVEM.W (A7)+,D0-D5/D7/A0-A6

MOVEM.W D0-D5/D7/A0-A6,-(A7)

Attributes: Size = word, longword

Description: The group of registers specified by is copied to

<register list>

or from consecutive memory locations. The starting location is

provided by the effective address. Any combination of the 68000’s

sixteen address and data registers can be copied by a single MOVEM

instruction. Note that either a word or a longword can be moved,

and that a word is sign-extended to a longword when it is moved

(even if the destination is a data register).

When a group of registers is transferred to or from memory

(using an addressing mode other than pre-decrementing or post-

incrementing), the registers are transferred starting at the specified

address and up through higher addresses. The order of transfer

of registers is data register D0 to D7, followed by address register

A0 to A7.

For example, moves registers

MOVEM.L D0-D2/D4/A5/A6,$1234

to memory, starting at location $1234 (in

D0,D1,D2,D4,A5,A6

which D0 is stored) and moving to locations $1238, $123C,... Note

that the address counter is incremented by 2 or 4 after each move

according to whether the operation is moving words or

longwords, respectively.

If the effective address is in the pre-decrement mode (i.e.,

), only a register to memory operation is permitted. The

-(An)

registers are stored starting at the specified address minus two

(or four for longword operands) and down through lower

addresses. The order of storing is from address register A7 to

address register A0, then from data register D7 to data register

The 68000's Instruction Set

36 D0. The decremented address register is updated to contain the

address of the last word stored.

If the effective address is in the post-increment mode (i.e.,

), only a memory to register transfer is permitted. The

(An)+

registers are loaded starting at the specified address and up

through higher addresses. The order of loading is the inverse of

that used by the pre-decrement mode and is D0 to D7 followed

by A0 to A7. The incremented address register is updated to

contain the address of the last word plus two (or four for longword

operands).

Note that the instruction has a side effect. An extra

MOVEM

bus cycle occurs for memory operands, and an operand at one

address higher than the last register in the list is accessed. This

extra access is an ‘overshoot’ and has no effect as far as the

programmer is concerned. However, it could cause a problem if

the overshoot extended beyond the bounds of physical memory.

Once again, remember that sign-extends words when

MOVEM.W

they are moved to data registers.

Application: This instruction is invariably used to save working registers on

entry to a subroutine and to restore them at the end of a

subroutine.

BSR Example

.

.

Example MOVEM.L D0-D5/A0-A3,-(SP) Save registers

.

.

Body of subroutine

.

.

MOVEM.L (SP)+,D0-D5/A0-A3 Restore registers

RTS Return

Condition codes: X N Z V C

- - - - -

Source operand addressing modes (memory to register)

The 68000's Instruction Set 37

Destination operand addressing modes (register to memory)

MOVEP Move peripheral data

Operation: [destination] [source]

Syntax: MOVEP Dx,(d,Ay)

MOVEP (d,Ay),Dx

Sample syntax: MOVEP D3,(Control,A0)

MOVEP (Input,A6),D5

Attributes: Size = word, longword

Description: The operation moves data between a data register and a

MOVEP

byte-oriented memory mapped peripheral. The data is moved

between the specified data register and alternate bytes within the

peripheral’s address space, starting at the location specified and

incrementing by two. This instruction is designed to be used in

conjunction with 8-bit peripherals connected to the 68000's 16-bit

data bus. The high-order byte of the data register is transferred

first and the low-order byte transferred last. The memory address

is specified by the address register indirect mode with a 16-bit

offset. If the address is even, all transfers are to or from the high-

order half of the data bus. If the address is odd, all the transfers

are made to the low-order half of the data bus.

Application: Consider a memory-mapped peripheral located at address

$08 0001 which has four 8-bit internal registers mapped at

addresses $08 0001, $08 0003, $08 0005, and $08 0007. The

longword in data register D0 is to be transferred to this peripheral

by the following code.

LEA $080001,A0

MOVEP.L D0,0(A0)

This code results in the following actions:

The 68000's Instruction Set

38 ←

[M(080001)] [D0(24:31)]

[M(080003)] [D0(16:23)]

[M(080005)] [D0(8:15)]

[M(080007)] [D0(0:7)]

Condition codes: X N Z C V

- - - - -

MOVEQ Move quick (copy a small literal to a

destination)

Operation: [destination] <literal>

Syntax: MOVEQ #<data>,Dn

Attributes: Size = longword

Description: Move the specified literal to a data register. The literal data is an

eight-bit field within the op-code and specifies a signed

MOVEQ

value in the range -128 to +127. When the source operand is

transferred, it is sign-extended to 32 bits. Consequently, although

only 8 bits are moved, the instruction is a longword

MOVEQ

operation.

Application: is used to load small integers into a data register. Beware

MOVEQ

of its sign-extension. The two operations and

MOVE.B #12,D0

are not equivalent. The former has the effect

MOVEQ #12,D0

← ←

[D0(0:7)] 12, while the latter has the effect [D0(0:31)] 12 (with

sign-extension).

The 68000's Instruction Set 39

Condition codes: X N Z V C

- * * 0 0

MULS, MULU Signed multiply, unsigned

multiply

Operation: [destination] [destination] * [source]

Syntax: MULS <ea>,Dn

MULU <ea>,Dn

Attributes: Size = word (the product is a longword)

Description: Multiply the 16-bit destination operand by the 16-bit source

operand and store the result in the destination. Both the source

and destination are 16-bit word values and the destination result

is a 32-bit longword. The product is therefore a correct product

and is not truncated. performs multiplication with unsigned

MULU

values and performs multiplication with two’s complement

MULS

values.

Application: multiplies the low-order words of data registers D1

MULU D1,D2

and D2 and puts the 32-bit result in D2. multi-

MULU #$1234,D3

plies the low-order word of D3 by the 16-bit literal $1234 and

puts the 32-bit result in D3.

Condition codes: X N Z V C

- * * 0 0

Source operand addressing modes

NBCD Negate decimal with sign extend

← 0 −

Operation: [destination] [destination] - [X]

10 10

Syntax: NBCD <ea>

The 68000's Instruction Set

40 Attributes: Size = byte

Description: The operand addressed as the destination and the extend bit in

the CCR are subtracted from zero. The subtraction is performed

using binary coded decimal (BCD) arithmetic. This instruction

calculates the ten’s complement of the destination if the X-bit is

clear, and the nine’s complement if X = 1. This is a byte-only

operation. Negating a BCD number (with X = 0) has the effect of

subtracting it from 100 .

10

Condition codes: X N Z V C

* U * U *

The Z-bit is cleared if the result is non-zero and is unchanged

otherwise. The C-bit is set if a decimal borrow occurs. The X-bit

is set to the same value as the C-bit.

Destination operand addressing modes

NEG Negate ←

Operation: [destination] 0 - [destination]

Syntax: NEG <ea>

Attributes: Size = byte, word, longword

Description: Subtract the destination operand from 0 and store the result in

the destination location. The difference between and

NOT NEG

instructions is that performs a bit-by-bit logical complemen-

NOT

tation, while a performs a two’s complement arithmetic sub-

NEG

traction. All bits of the condition code register are modified by a

operation. For example, if D3.B = 11100111 , the logical op-

NEG 2

eration results in D3 = 00011001 (XNZVC=10001) and

NEG.B D3 2

= 00011000 (XNZVC=-0000).

NOT.B D3 2

Condition codes: X N Z V C

* * * * *

Note that the X-bit is set to the value of the C-bit.

The 68000's Instruction Set 41

Destination operand addressing modes

NEGX Negate with extend

Operation: [destination] 0 - [destination] - [X]

Syntax: NEGX <ea>

Attributes: Size = byte, word, longword

Description: The operand addressed as the destination and the extend bit are

subtracted from zero. is the same as except that the X-

NEGX NEG

bit is also subtracted from zero.

Condition codes: X N Z V C

* * * * *

The Z-bit is cleared if the result is non-zero and is unchanged

otherwise. The X-bit is set to the same value as the C-bit.

Destination operand addressing modes

NOP No operation

Operation: None

Syntax: NOP

Attributes: Unsized

Description: The no operation instruction, performs no computation.

NOP

Execution continues with the instruction following the NOP

instruction. The processor's state is not modified by a .

NOP

The 68000's Instruction Set

42 Application: s can be used to introduce a delay in code. Some programmers

NOP

use them to provide space for patches — two or more s can

NOP

later be replaced by branch or jump instructions to fix a bug. This

use of the is seriously frowned upon, as errors should be

NOP

corrected by re-assembling the code rather than by patching it.

Condition codes: X N Z V C

- - - - -

NOT Logical complement

Operation: [destination] [destination]

Syntax: NOT <ea>

Attributes: Size = byte, word, longword

Description: Calculate the logical complement of the destination and store the

result in the destination. The difference between and is

NOT NEG

that performs a bit-by-bit logical complementation, while a

NOT

performs a two’s complement arithmetic subtraction. More-

NEG

over, updates all bits of the CCR, while clears the V- and

NEG NOT

C-bits, updates the N- and Z-bits, and doesn't affect the X-bit.

Condition codes: X N Z V C

- * * 0 0

Source operand addressing modes

OR OR logical

Operation: [destination] [source] + [destination]

Syntax: OR <ea>,Dn

OR Dn,<ea>

Attributes: Size = byte, word, longword

The 68000's Instruction Set 43

Description: OR the source operand to the destination operand, and store the

result in the destination location.

Application: The instruction is used to set selected bits of the operand. For

OR

example, we can set the four most-significant bits of a longword

operand in D0 by executing:

OR.L #$F0000000,D0

Condition codes: X N Z V C

- * * 0 0

Source operand addressing modes

Destination operand addressing modes

ORI OR immediate

Operation: [destination] <literal> + [destination]

Syntax: ORI #<data>,<ea>

Attributes: Size = byte, word, longword

Description: OR the immediate data with the destination operand. Store the

result in the destination operand.

Condition codes: X N Z V C

- * * 0 0

Application: forms the logical OR of the immediate source with the

ORI

effective address, which may be a memory location. For example,

ORI.B #%00000011,(A0)+

The 68000's Instruction Set

44 Destination operand addressing modes

ORI to CCR Inclusive OR immediate to CCR

Operation: [CCR] <literal> + [CCR]

Syntax: ORI #<data>,CCR

Attributes: Size = byte

Description: OR the immediate data with the condition code register (i.e., the

least-significant byte of the status register). For example, the Z

flag of the CCR can be set by .

ORI #$04,CCR

Condition codes: X N Z V C

* * * * *

X is set if bit 4 of data = 1; unchanged otherwise

N is set if bit 3 of data = 1; unchanged otherwise

Z is set if bit 2 of data = 1; unchanged otherwise

V is set if bit 1 of data = 1; unchanged otherwise

C is set if bit 0 of data = 1; unchanged otherwise

ORI to SR Inclusive OR immediate to status

register

Operation: IF [S] = 1

THEN ←

[SR] <literal> + [SR]

ELSE TRAP

Syntax: ORI #<data>,SR

Attributes: Size = word

Description: OR the immediate data to the status register and store the result

in the status register. All bits of the status register are affected.

The 68000's Instruction Set 45

Application: Used to set bits in the SR (i.e., the S, T, and interrupt mask bits).

For example, sets bit 15 of the SR (i.e., the trace

ORI #$8000,SR

bit).

Condition codes: X N Z V C

* * * * *

X is set if bit 4 of data = 1; unchanged otherwise

N is set if bit 3 of data = 1; unchanged otherwise

Z is set if bit 2 of data = 1; unchanged otherwise

V is set if bit 1 of data = 1; unchanged otherwise

C is set if bit 0 of data = 1; unchanged otherwise

PEA Push effective address

← ←

Operation: [SP] [SP] - 4; [M([SP])] <ea>

Syntax: PEA <ea>

Attributes: Size = longword

Description: The longword effective address specified by the instruction is

computed and pushed onto the stack. The difference between

and is that calculates an effective address and puts it

PEA LEA LEA

in an address register, while calculates an effective address

PEA

in the same way but pushes it on the stack.

Application: calculates an effective address to be used later in address

PEA

register indirect addressing. In particular, it facilitates the writing

of position independent code. For example, )

PEA (TABLE,PC

calculates the address of with respect to the PC and pushes

TABLE

it on the stack. This address can be read by a procedure and then

used to access the data to which it points. Consider the example:

PEA Wednesday Push the parameter address on the stack

BSR Subroutine Call the procedure

LEA (4,SP),SP Remove space occupied by the parameter

.

Subroutine MOVEA.L (4,SP),A0 A0 points to parameter under return address

MOVE.W (A0),D2 Access the actual parameter — Wednesday

.

RTS

Condition codes: X N Z V C

- - - - -

The 68000's Instruction Set

46 Source operand addressing modes

RESET Reset external devices

Operation: IF [S] = 1 THEN

Assert RESET* line

ELSE TRAP

Syntax: RESET

Attributes: Unsized

Description: The reset line is asserted, causing all external devices connected

to the 68000’s RESET* output to be reset. The instruction is

RESET

privileged and has no effect on the operation of the 68000 itself.

This instruction is used to perform a programmed reset of all

peripherals connected to the 68000's RESET* pin.

Condition codes: X N Z V C

- - - - -

ROL, ROR Rotate left/right (without extend)

Operation: [destination] [destination] rotated by <count>

Syntax: ROL Dx,Dy

ROR Dx,Dy

ROL #<data>,Dy

ROR #<data>,Dy

ROL <ea>

ROR <ea>

Attributes: Size = byte, word, longword

Description: Rotate the bits of the operand in the direction indicated. The

extend bit, X, is not included in the operation. A rotate operation

is circular in the sense that the bit shifted out at one end is shifted

into the other end. That is, no bit is lost or destroyed by a rotate

The 68000's Instruction Set 47

operation. The bit shifted out is also copied into the C-bit of the

CCR, but not into the X-bit. The shift count may be specified in

one of three ways: the count may be a literal, the contents of a

data register, or the value 1. An immediate count permits a shift

of 1 to 8 places. If the count is in a register, the value is modulo

64, allowing a range of 0 to 63. If no count is specified, the word

at the effective address is rotated by one place (e.g., ).

ROL <ea>

Condition codes: X N Z V C

- * * 0 *

The X-bit is not affected and the C-bit is set to the last bit rotated

out of the operand (C is set to zero if the shift count is 0).

Destination operand addressing modes

ROXL, ROXR Rotate left/right with extend

Operation: [destination] [destination] rotated by <count>

Syntax: ROXL Dx,Dy

ROXR Dx,Dy

ROXL #<data>,Dy

ROXR #<data>,Dy

ROXL <ea>

ROXR <ea>

Attributes: Size = byte, word, longword

The 68000's Instruction Set

48 Description: Rotate the bits of the operand in the direction indicated. The

extend bit of the CCR is included in the rotation. A rotate

operation is circular in the sense that the bit shifted out at one

end is shifted into the other end. That is, no bit is lost or destroyed

by a rotate operation. Since the X-bit is included in the rotate, the

rotation is performed over 9 bits ( ), 17 bits ( ), or 33 bits ( ).

.B .W .L

The bit shifted out is also copied into the C-bit of the CCR as well

as the X-bit. The shift count may be specified in one of three

ways: the count may be a literal, the contents of a data register,

or the value 1. An immediate count permits a shift of 1 to 8

places. If the count is in a register, the value is modulo 64 and the

range is from 0 to 63. If no count is specified, the word at the

specified effective address is rotated by one place (i.e., ).

ROXL <ea>

Condition codes: X N Z V C

* * * 0 *

The X- and the C-bit are set to the last bit rotated out of the

operand. If the rotate count is zero, the X-bit is unaffected and

the C-bit is set to the X-bit.

Destination operand addressing modes

RTE Return from exception

Operation: IF [S] = 1 THEN ← ←

[SR] [M([SP])]; [SP] [SP] + 2

← ←

[PC] [M([SP])]; [SP] [SP] + 4

ELSE TRAP

The 68000's Instruction Set 49

Syntax: RTE

Attributes: Unsized

Description: The status register and program counter are pulled from the stack.

The previous values of the SR and PC are lost. The is used to

RTE

terminate an exception handler. Note that the behavior of the

instruction depends on the nature of both the exception and

RTE

processor type. The 68010 and later models push more informa-

tion on the stack following an exception than the 68000. The

processor determines how much to remove from the stack.

Condition codes: X N Z V C

* * * * *

The CCR is restored to its pre-exception state.

RTR Return and restore condition codes

← ←

Operation: [CCR] [M([SP])]; [SP] [SP] + 2

← ←

[PC] [M([SP])]; [SP] [SP] + 4

Syntax: RTR

Attributes: Unsized

Description: The condition code and program counter are pulled from the

stack. The previous condition code and program counter are lost.

The supervisor portion of the status register is not affected.

Application: If you wish to preserve the CCR after entering a procedure, you

can push it on the stack and then retrieve it with .

RTR

BSR Proc1 Call the procedure

. .

. .

Proc1 MOVE.W SR,-(SP) Save old CCR on stack

. .

. Body of procedure

. .

RTR Return and restore CCR (not SR!)

Condition codes: X N Z V C

* * * * *

The CCR is restored to its pre-exception state.

The 68000's Instruction Set

50 RTS Return from subroutine

← ←

Operation: [PC] [M([SP])]; [SP] [SP] + 4

Syntax: RTS

Attributes: Unsized

Description: The program counter is pulled from the stack and the previous

value of the PC is lost. is used to terminate a subroutine.

RTS

Condition codes: X N Z V C

- - - - -

SBCD Subtract decimal with extend

Operation: [destination] [destination] - [source] - [X]

10 10 10

Syntax: SBCD Dy,Dx

SBCD -(Ay),-(Ax)

Attributes: Size = byte

Description: Subtract the source operand from the destination operand together

with the X-bit, and store the result in the destination. Subtraction

is performed using BCD arithmetic. The only legal addressing

modes are data register direct and memory to memory with

address register indirect using auto-decrementing.

Condition codes: X N Z V C

* U * U *

Z: Cleared if result is non-zero. Unchanged otherwise. The Z-bit

can be used to test for zero after a chain of multiple precision

operations.

Scc Set according to condition cc

Operation: IF cc = 1 THEN [destination] 11111111

2

ELSE [destination] 00000000

2

Syntax: Scc <ea>


PAGINE

58

PESO

822.22 KB

AUTORE

flaviael

PUBBLICATO

+1 anno fa


DETTAGLI
Corso di laurea: Corso di laurea in ingegneria informatica
SSD:
A.A.: 2013-2014

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher flaviael di informazioni apprese con la frequenza delle lezioni di Architetture Sistemi Elaborazione e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università Napoli Federico II - Unina o del prof Mazzocca Nicola.

Acquista con carta o conto PayPal

Scarica il file tutte le volte che vuoi

Paga con un conto PayPal per usufruire della garanzia Soddisfatto o rimborsato

Recensioni
Ti è piaciuto questo appunto? Valutalo!

Altri appunti di Architetture sistemi elaborazione

Architetture Sistemi Elaborazione – Interruzioni
Dispensa
Architetture Sistemi Elaborazione   - Sommatori ASE
Dispensa
Architetture Sistemi Elaborazione -  Moltiplicatori sequenziali unsigned
Dispensa
Architetture Sistemi Elaborazione – Intel
Dispensa