Appunti electronics systems (parte 4)

1) Lecture -

Modern their

electronic systems and

digital electronic implementation

mainly

· systems

are ,

family logic

technological

the realize and

depends to

used gates circuits

on .

Digital historically

have

electronic familie

been implemented logic

different

systems

· using

l3 : Transistor =>

Diode

D Logic.

TL : . bipolar

* transistor

diode-

Transistor

Resistor Logic .

RTL : Transistor

Transistor

TTL Logic .

:

In In

the

DTL logic while the

diodes perform switch

transistor

· acts mainly

operation as a .

, transistor logic

In

to imple

driving

used

RTL before

resistors combine inputs TTL is

are .

a

, , .

transistors

mented bipolar

entirely using .

technologies fundamental

Although these development

the digital

· they

early circuits

of

in

were ,

from

suffer :

significant dissipation

power .

heat generation .

scalability

poor .

limited integration density .

This technology

to

motivated the transistor

· CMOS .

Semiconductor)

CMOS/Complementary best technological

the

Metal-Oxide for

family

· is

-

integrated circuits

.

The Key

· reasons are : .

resistors

No used

are

heat

dissipated

Less .

Very dimensions

transistor

small . (VLSI) 10

Integration

Scale than

with

Enables Very Large transistors

more .

.

(sensor

chip logic)

digital

Allows complete single

systems ADC

on a ,

,

transistors

· CMOS built there two types

and

circuits MOSFET

using are

are :

,

MOS

n - MOS

p-

The schematic shows

· the complementary structure

gate

CMOS NAND :

.

I network)

transistors to

connected Vac pull-up

MOS

p- network

/

connected to

transistors pull-down

GND

MOS

n- behavior

complementary

This low

· the static

key since

CMOS

is very

consumes

reason power cur

,

switching

flows

ideally

rent only during .

CMOS charging but

transistor

miniaturization

· supports behavior

technology extreme by

not ,

, transistore

by of

number

which the

allows to

the manufacturing

improving expo

grow

process ,

nentially .

Advantages scaling

of include :

Larger for

transistors silicon

number the

of same area

Chip proportional to silicon

> cost cost reduction

is area .

Lower supply voltage

to lower

Leads consumption

power .

logic

More compact gates

Shorter lower

distances

> delay

propagation

s .

higher

Enables frequencies

clock . Integration) (Very

( Scole

Small

Over the to

evolved love

· from

digital SSI VISI

circuits

years , (

Scale Integration

ge

As integration increased became

manual impossible

design

circuit

, .

During hand

these design

to

from automated

· design

moved

digital made

design

result

years as a

, , ,

Tools

EDA) Design

Electronic

by Automation

possible

An integrated defined

circuit is as :

" the entire the

implemented silicon

circust water

of

piece

same

on

Each The

silicon following

processed procedure

photolithography the

· water is

is using :

.

the

A the

defining placed

layout

mask circuit water

is over .

light

UV selected regions

exposes .

Exposed chemical

undergo processes

areas .

and

This interconnections

transistor geometry

defines

sequence .

the

layout

This from the

design photolithographic

generated

· directly determines maske

process .

Languages)

I

The automated Description

Hardware

relies

digital HDL

design HDL

· of :

on .

hardware

Describes not software .

,

the

Defines behavior

and

structure of circuits

.

technology independent

Is

Is and

for

both

used testing

design .

code translated

HDL

· physical

ultimately into circuit

is a .

There (abstraction)

three levels HDL-based design

representation

· in

are :

Level)

/Register

RTL Transfer

.

1 provides

RTL abstract description of

terms

of circuit in

an a :

Registers

.

i Logical operations performed from registers

signals

ii

. on .

level

this

At :

Registers functional

represented by symbols

i are .

. loxes

by

Complex with outputs

represented

operations and

inputs

ii

. generic .

are )

(AND

Simple logic gate-level

operations symbols

NOR

iii. NAND

NOT use

...

,

,

, ) …

functional

functional symbol NOR

AND

NOT

of

symbol of function

generic

register

examples

· The longest achievable frequency

design the

combinational determines

· path clock

maximum

in a

level)

/Gate

level

Logic

2 . level

At this described

· the circuit is as :

,

AND gates

OR NOR

NAND

NOT , .

,

, ,

Interconnected functions

to implement logic .

.

3 Transistor Level

level shows

This

· :

Actual transistors .

Electrical connections .

Physica realization

.

Lower levels higher choose

but Designer the

must

complexity

· al

appropriate

give more accuracy .

,

level .

straction Va

Vac ... - .....

signal

A interpreted

· is as : he

Hi -------

hold

Logic high threshold

the

"I" if above Unknown

. Low--------

Logic the low

below threshold

"O" .

if threshold

between threshold

if

Unknown O

. O …

- …

…

cleanly

The thresholds undefined time

clock signals

· must avoiding Over V

regions

cross

ensure . ,

,

from

scaled reducing

to consumption

down V

5V 9 power

-0 .

. ,

An behaves controlled

like switch

transistor

· n-MOS a :

I

Drain

, =:

V

Vos ?

·

{

+ V

Vag > ) ·

> =

¤ ↓

{ Voltage

Gate-Source S

threshold

Voltage

If

· : "closed

Vt switch

Vas ? switch

Vf

Vas > " open

Important

· constraints :

Vcc VI

?

10

V

+

Ve the applied

the the

· circuit

parts

supply to all of

voltage s voltage

is maximum

is .

D

G

L . => Vas =:

VecV

=

+

Vos {

_ D

δ

O = .

VOS =

Vf

OVE

≈

ㅏ

Vos S

{

_

The dual

the control

behaves

of with

the oppositely respect to

· voltage

it

p-MOS n-MOS

is meaning ,

,

in CMOS .

D ω

sG

I +

Vos S

{

_ D

G ω

ㅓ ω

Vos S

_

To understand how digital ladder

the abstraction

conceived

· systems from

modeled

and start

we

are ,

that and

microelectronies

involved

fields

together the

links different computer

all engineering

in .

diagram hierarchy

This from

· shows the physics

abstraction

of to this ladder defines

software ;

involved microelectronic

the systems

embedded

modern and

domains in .

level

lowest to

deal

the physical

electrons behavior then

and transist

with

At

· we we move up

,

,

tors software-level

and architectural

and

analog finally

digital and

to

gates

logic

circuits can

, ,

, sets

like and essential

This comple

abstraction

instruction to

cepts application is manage

programs .

specialization

and

xity .

↑· · · (

In Language)

this Hardware

HDL Description It

context crucial role

· plays operates speci

a .

, level

between level

fically the

the designers

This

and to

gate

system . descri

allows

HDL

means =

be high-level enough low-level

but enough

to

circuits to

complexity

that's

in way manage

a ,

hardware

mapped

be physical

onto .

Complexity layers

managed

is across :

System behavioral

Level high-level transactions

models

: .

,

Levell

C described nets

architecture and

Register register

RTL logic connections

Transfer with

: .

physical

Gate Level mapped library

to cells

: .

schematic

Level

Transistor of transistors

: . chip fabrication

Level

Geometric for

actualsilicon masks

: .

When designing to

function f(x) hardware

such decide

· different

algorithm onto

it

we

as can

a or map

,

,

targets platforms

The target

HDL

using main are :

. Microcontrollers)

/General Processors

Purpose

.

1 C

EPP :

and

Flexible generic . Architecture

ISA) Instruction

full Set

with

Come a because

efficient have

they logic

general-purpose that's not

for custom

Not applications op

timized

. to

used behavior

external control

with

Typically software .

Intel

Examples RISC-V

AMS ARM

: .

,

, , Processors/System-on-Chip

(Digital Signal

DSP

2

2 SoC dedicated

and

approach components

logic

include

Hybrid general-purpose

some come .

:

signal

Target tasks systems

embedded

processing or .

Xilinx

Common Contex

platforms M Zyng

TMS320 ARM

: -

, ,

Arrayl

(

3

. Programmable

FPGA Field Gata (CLBs)

Reprogrammable chips embedded

logic

composed blocks

configurable

of memo -

,

RAM) I/O

(ROM units and blocks

DSP

ries , .

, ,

connected

All programmable matrix

interconnection

via a .

how arranged

diagram

This show matrix connected

· through

and interconnection

CLBs in

are a

lines .

Advantage to

like

the

· custom circuit committing actual

before

act

to

FPGA

can

you

: program a ma

facturing

no . (200

for

Used automotive medium

applications and production

prototyping small

,

space

s runs

units)

1000

- .

Examples Xilinx Spartan Cyclone

Stratix

Virtex

· Altera

: , .

(Application Circuit

4 Integrated

ASIC Specific

. for

Final destination designs

many .

Semi-Custom built array)

standard

from library (e

ASICs cells gate

g

: .,

. highest

level

ASICI designed for

manually transistor

Full-Custom at officiency

: I

Require foundry for right target

the

shown

from HDL

silicon

design dia

the of

Kit in

a

a

gram) . flexibility

Each needs

targets different

these and

cost

of performance volume

· influe

all

serves : , ,

,

choice to from

the

the them

HOL entry to algorithm

all

point of

ence serves common way move

as a

.

implementatio

physica

to n. described

About be

they around

structured

· semiconductor

FPGAs devices matrix of resources

as

can a

, I/O)

(logic connected by interconnects

programmable

all

DSP

memory

, .

,

, ,

characteristics

The

· Key of FPGAs are :

They fabrication

reprogrammable after

even

ar .

how

Their defines

configuration wired together

resources are .

You chip fabrication

without

simulate test

and

design it

then real

can your on a .

Ideal for where

automotive

environments

control need

and

especially is

in reprogramming

aerospace

, ,

.

ed for

Cheaper than low

ASICs volume production .

rrinzz

This for constrained

deployment

practical

them

· platform levelopment

makes and

testing in

even

a ㅇ _

, ,

applications

.

*

· testing

HDL also crucial for for them

· designs not writing

just

is , .

A Process structured

typically following

Circuit

· the

Design steps

is in :

?

Define the the

should

What

requirements do

circuit

.

1 :

Design the high-level architecture

.

2 identify the blocks their outputs

inputs

main

: , .

break

.

3 Partition submodules manageable

into into components

down

: .

4 and test

Design blocks

individual

. .

blocks to interaction

testing

integration

Combine and verify

perform

5

5 .

.

6 hardware

Final deployment validation real

and on .

This structured both correctness and scalability

process ensures .

As module

Each

to the

actual code module

the

writing Verilog

· unit Sy