Estratto del documento

D

무 rIDS

③ ℃

characteristics : 、

V

. 0

i p

+ (Off)

Vip

Vo Jos O

ii. =

> ~ (ON)

IdS

Vip

Vos =

iii. = o

<

triode and

two saturation

· regions :

In practice connected to

S Vac

is so :

, switch

Vo Vec

. = OFF

i = switch

Vo

ii. = ON

0

= ?

cos'é

Applying Vas-Vos

obtain Vap

KVL we =

The fundamental

the building

gate digital

block It

CMOS logic

· of

NOT is uses com

a

.

plementary and that

such when

connected

of transistors nMOS

pMOS in

pair way

one one a

-

high the and

low

input

the output vice

is is versa

.

, ,

connected to

terminal of

↑ + supply

voltage

Vec

A

b of pMOS

S > source it's

because

D can -

Inspected theh

to

~

Vin Vout

·

IDSn

G D of MOS

source

s > it's

because con=

nected ground

to

TGNs

↳ connected to -

of

terminal po

=

supply

were

Because there's Also

· have

load connected Issp

to applying

output -Issn

KCL = we see

we can

no , .

that :

{ ground

I the to

potential connected

because of

Vin Vin

Vasp is IN

=

VaSN Vin-Voc

= is Vosw

Vovta 羹

“ ‰

Issn lssu

[osp

1

1 Vosp

=> =

0 0

0

= = = =

-

nEosp

>Vosp

o ☆ connected to

output Voc

pMOS is

ON OFF

is nMOS

,

Both transistors between

2 two

the

flowing

current

ON s

are

. .

Initially ground

output to

strongly then to

pulls

pulls

pMOS MOS

Vec

: .

,

Output from .

to

Ve ground

moves Vosn

.

3 )

Issp lssn

=>

0 = o

0

= =

=

Tos na Vasen connected ground

to

ON-output

nMOS

~ pMOS OFF ,

5VsSm

50Lecture

Like fundamental

simplest

before but

the

said gate

the

gate

· NOT

CMOS is

we ,

,

inverter

or .

二 VcC

a vIc

ViN VouT

. ·

A inverter composed

CMOS transistors

complementary

· two

of

is :

transistor the top

connected to V

pMOS on

a ground

connected to bottom

the

the at

nMOS

an

the applied both

the

input terminals

gate

to

voltage simultaneously

Vin transistores

of

is

the between them

node

from the

output taken

Yout

volage is .

VoUT

uMOS

Vin pMOS VcC

N

OFF

Vac OFF

ON O

The idea behavior

Key complementary

· is :

low

When (0)

the to

the output

the

and

input pulled

pMOS is

MOS

is OFF

is ON is up

,

VEC . (Voc)

high

the the and output down

When the

input off pulling

MOS pMOS

ON

is

is is s

,

.

to ground

This that both

transistor This

only

logic

steady conducts

conditions

· in

means never

one , .

complementary extremely

operation two important properties

produces :

full Logic's

CMOS reaches

logic the

guarantees for

exactly and

output Vec

swing :

a le

families

Unlike degraded

logic

for there

older TTL

'O

GNS voltage

MOS is

or no

,

.

vel .

The because there

static current negligible direct conductive

states

stable

is in is po

no

,

between

th and

Vcc GND .

:Prosor

#Moscow Ix

α , 簒

Ic …

… …

max

วย" "Vin

Vi ㅇ

Vip

Vin Vec +

The first threshold whi

shows

diagram

· the

smooth the

transition input region

crosses

as

a ;

le the both

where

showe tran

switching

second the

only

current peak region

in

one a ,

Outside this the

essentially

partially the

sistors current

ON is

region :

zero

are . ,

output .

stable

is

In regardless

general function built two comple

of logic

· gate its

CMOS is using

every ,

, ,

transistor

mentary networks :

Pull-Up

The made role

of

Network whose

exclusively to the

connect out

transistors

pMOS is

: , -

put to Vac . ground

Pull

The Which

made the

transisters output to

Down Networki connects

of MOS .

,

Vac

·

PUN

VA VouT

·

. &

VB PDN

. ㅇ GND

This both

diagram feeding networks

· shows output

simultaneously

the

visually inputs with node

the

,

placed between and PDN

PUN

ช่ The operating following

rules the

· are :

A When input LOW

its

pMOS ON

turns is HIGH

An When inpot

turns its

nMOS ON is .

The networks constructed and

· they

parallel always

connections

and

using series

are com

are

,

plementary :

transistors

If they the

be

will

the parallel

PDN PUN

in

in in in

series

are , .

If they the

be

the

parallel they will

PDN PUN

in in in

series

in

are ,

This like

that

guarantees behaves short

for

· combination

input network

possible

every one a

,

the

While behaves

other like circuit

circuit open

an .

, logic

This fundamenta and

safe

the Why

· logically correct

efficient

is CMOS is powers

reason , .

, both

let's introduce

this

After logic theory outputs when

· From

gate gate only

NAND O

NAND

a , a

, .

inputs the

other

all output

in

1 is .

1

are cases

; ,

B

A NAND

A . . . %

0 1

· 1 I

ㆁ 아

I I ㅇ

오 behavior

the transistor level implemented

At this naturally

· is CMOS

in .

very

, Vec

* PUN

(parallels(

MP

MPA β VouT

A PDN

MnA

o Iseries(

VB Muß

The becaus high

PDN with

· turn

transistors

two transistors

of

consits ON

MOS in

in

MOS series a

both ground

when and path

equal

put short

and conducts creating

the only

PDN to

B toa

A are a .

hand

,

other made

the

The Since

two parallel

of .

PUN transistors

· pMOS

is pMOS in

on

,

devices low

turn least

input input the transistors

With if of

at O

ON pMOS

is one

one

a ,

,

conducts the

and output to

pulls Vec

up MaB Vout

Maa

VA VB MpA Mpr Voc

ON ON

OFF OFF

O

ㅇ Vac

V

O OFF

ON

OFF ON Voc

V O OFF ON

OFF

ON

V

V OFF OFF O

ON

ON

Walking through the

· cases :

If While

B completely

A PUN completely

and PDN VouT Vec

So

ON

0 0 is

is OFF

= =

= , I

If open)

broken

only but

the the

path

still

PDN

input still

PVN

I is series

is

one can

, ,

through branch

ducts Vec

Vout

a =

If and

A completely

PDN

B YouT

While So

PUN completely

1 1 O

is ON Off

is

= =

= , .

The both

dual

logical the

gate when

only

the of inputs

outputs

NOR it

NAND I

is are

,

∅ B NOR

A

A ㆁ I

oO

β ㆁ

1 ± ㅇ

1

Here the network structures the

reversed compared

· to .

NAND

are

Vec PUN

VA MPA VB

Va VoUT

Mpa

MuB

Maa MPB ±

ㆀ ON

OFF OFF ON

VB MPB Ve OFF O

. OFF

0 ON

ON

VO OFF ON

OFF

ON ㆁ

VoUT

④ V V ON

ON O

OFF

OFF

VA MnA Mmß · VB

PDN

The made

PUN that both

of two

· transistors must be

and B

A

pMOS in series

is meaning

,

the

connect

LOW output to Vec

to .

The the

of

made parallel

transistors

two HIGH

just

PDN

· of input

nMOS

is in so one

presence

,

.

to

enough to

the output

pull down

is ground

According the high

the both

to single

truth where

table output the

only inputs

· is in case are

,

others

low

low all

and in .

, let's but lo

important The

consider complex

Now the gate

structure AOI

CMOS

more very

a : .

function is

gic : )

{

)

(

Y B

B C

A + .

に .

Voc

ie Ve

VA VB

PUN

Va Mma Muc ve

风 VB Vo

Muß Mus PDN

V

The when

be

the

activated when that This

output

· PDN LOW

must AB CD

is is

1 .

1

is = =

or

,

branch

branches

implemented parallel each containing two

two transistors in

nMOS

using in series ·

,

The complementary branches each branch

PUN two

the made

network two

of

· is in series

: ,

.

transistors parallel

pMOS in

This complementary behavior while to

logic

construction transistors

· correct only B

using in

ensures

which extremely efficient

tal compact

gates and

makes AOI .

, had

to

Up only

gates

all two

· states

output real digital mul

systems

However in

0 .

1

now : Or ,

,

,

tiple share buses

lines called

often data

circuits common .

,

iN OUT

OwT C

iN .

. Impedence

(High

Z

ㆀ writes

E 。 reads from

1 □ Z buffer

from ↓

buffer

110 } C E

same as

< a

gate

buffer ìn in

our OUT

LOGiC LOGiC

If two bus

try driving High and

the other

the time

drive

to at the

circuits

· same one

same - damage

called

condition and

bus possible

connection current

LOW excessive

causing

occurs .

a , while

only

this others

avoid driver moment

the

must must

all

bus at

connected

be

To

· to

one any

, leads called

This

electrically third

disconnect state

from the output

to

it introduction of

. a ,

(2)

High-Impedance

Electrically law

flows

· Ohm's obtain

current

I Using we

means no :

.

, I

B Rs

. =

0

: I ∞

high-impedance

So behaves physically

gate removed from bus

the

· output the

if is .

a as

tri-state logic three

that produce

A This

gate gate output

· states and

0

is is

z

1

can : a

a .

,

,

chieved signal

introducing

by control C

a .

iN C OUi

pbwt

iN . Z

0

-

C β

。 어 ㆁ

whatever 1

£

1

the

is

input

the

both

When disabled and and

and both transistors

· PUN PDN

and PMOS

C MOS

0 off

= are are ,

, high-impedance

the the

output state

enters z

.

behaves

When like

the gate normal

exactly inverter

· C 1 CMOS

= :

a

,

If Vout

IN 0

0

= =

If IN Vort

1 1

= = VC Un

Vp Ma

Ve

Vin Mp Vout

a

p 0 OFF

Vcc

O OFF Z

O

Vin ep VecO OFF

OFF

Vo O Z

Vo

.

C N

. · Vcc Vcc

Vcc O

0 OFF ON

Un Vcc

pem Vcc OFF

Vcc O ON

O

Va GATE

NOT Veel

(When

(When Vee)

get

To and

need

output

· O Mn

Up

Mp Un

OFF ON

we =

on =

0) 0)

ON (Vp OFF(Vn

need

get and

output

To Mr

Vec Mp

on we =

=

state)

(high-impedance

When the impact

Va the

through

current gate

· 0 is 0 >no

= ,

(no .

gate

the the

of bus impact)

voltage

on * Ve from

Vo disconnected the bus

· .

. vo = flow

No current

· .

BUS

VGNO

6o Lecture

Static behavior and

function steady-state

logic

logic levels

logic

defines

gate its

of CMOS ope

a , ,

and

However inputs

digital

real do

time operate

gates

with

circuits

ration not in iso

in vary

. ,

, .

lation . logic

and

Each by

both famil

driven

gate drives gate

gates the

other another of

· CMOS is s

Anteprima
Vedrai una selezione di 7 pagine su 30
Appunti Electronics systems (parte 2) Pag. 1 Appunti Electronics systems (parte 2) Pag. 2
Anteprima di 7 pagg. su 30.
Scarica il documento per vederlo tutto.
Appunti Electronics systems (parte 2) Pag. 6
Anteprima di 7 pagg. su 30.
Scarica il documento per vederlo tutto.
Appunti Electronics systems (parte 2) Pag. 11
Anteprima di 7 pagg. su 30.
Scarica il documento per vederlo tutto.
Appunti Electronics systems (parte 2) Pag. 16
Anteprima di 7 pagg. su 30.
Scarica il documento per vederlo tutto.
Appunti Electronics systems (parte 2) Pag. 21
Anteprima di 7 pagg. su 30.
Scarica il documento per vederlo tutto.
Appunti Electronics systems (parte 2) Pag. 26
1 su 30
D/illustrazione/soddisfatti o rimborsati
Acquista con carta o PayPal
Scarica i documenti tutte le volte che vuoi
Dettagli
SSD
Ingegneria industriale e dell'informazione ING-INF/01 Elettronica

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher ingchiaretta98 di informazioni apprese con la frequenza delle lezioni di Electronics systems e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università Università degli Studi di Pisa o del prof Baronti Federico.
Appunti correlati Invia appunti e guadagna

Domande e risposte

Hai bisogno di aiuto?
Chiedi alla community