Appunti Electronics systems (parte 3)

The Program the address

IPC) the

to

whose role

Counter of

store instruction currently

is

,

It the address

being by

. updated

continuously depen

instruction generator

executed is .

type (sequential

ding branch

the the execution call return)

of instruction

on ,

, ,

(IR)

Instruction

The fetched

which temporarily from

instruction

Register the

stores in

, because

fundamental from

The decisions originate

control

IR

struction all

is

memory y field

opcode

decoding .

its

The which the

File

Register the fast It

the contains

storage inside

main

is ope

.

processor

,

needed

rande by decoding

and and write-back

accessed during

instructions is . ad

which

The performs logical and

operations

arithmetic operations

ALU also

comparisons

,

, ,

,

computations

dress .

Instruction

The address computes the the

which next value of

generator PC .

,

Processore

The by

which the execution control

entire generating

interface signals

supervises

memory .

,

The simplest to

architecture single-cycle

implement each

Where

architecture

· instruc

is a ,

tion clock cycle

entirely

completes within one . t +co +polmax

ttteo t

+

+

+ su

tpolmax

Conceptually data (such

from through

start

· network

logic

combinational

register

source pass a

a

, ,

ALU) cycle

and destination

the into within

back the

written register same

as are a .

, the

triggers data registers

edge then

sampling

the clock into

input

According the

to of

diagram

· ,

the the

before

the edge

which

combinational clock

must stabilize

computes ,

network output so

that be stored the

it destination registers

in

can .

However for

three the

timing

correct flip-flops

satisfying constraints

operation Key

· requires

, :

(tcol the

from clock

delay the output

Clock-to-output valid

edge until the .

register

of is

: source

Itelma

combinationa through

delay net.

combinational

the

delay

Maximum Worst propagation

: case

Work . (tsu)

Setup time time the which

clock

before during

next edge destination

the input the

of

:

be

must stable.

register

cLK t

皆 T

+

…

:

ii

im

taw

From the timing diagram clock period

the

· must satisfy :

, [su't

t ten-Apolma

teo

teo telmax

+ TI

=>

T

+

+ polmax + + +

Thus that

limited

the by

frequency This

longest

· the

clock if

the system

path

data

maximum in

is means

.

,

the combinational clock period

network becomes complex performance

reducing

the must increase

, .

,

To the clock clock frequency the

and the

reduce logic

· combinational

period increase can

,

be blocks leads to

This

split smaller multi-stage

into by

separated

multipl registers a

.

architectura

In multi-stage multiple

proceeds

design cycles

clock

· intermediate

computation with

over r

a ,

, operation and ideally

part

Each

stages stage

stored the

between

sults of

registers performs

in . a ,

balanced

the stages that

delays the

of so

are :

,

Apol benefit

tpoly-Apoa-Apos lose the from

otherwise multi-stage

= .

> we

If tpoltco tool and superseded valid

this delay

that

approximation

to the

· T2 of DFF is on

,

3

ly limited to

for tco the

due

delay interconnections

to and

number otherwise matter

stages

of .

a , ,

Importantly to

architecture next

instruction if

only the

· stage

multi-stage

in can

an move

a

,

the has frequency

completed clock

latency

stage but

previous improves

increases

so .

, ,

further

A different diffe

pipelining where stages

improvement simultaneously

operate

· is , on

Instead to

rent for starting

befor

of waiting stages

complete

instruction

instructions all

. one

the advances by

cycle

each

next clock stage

instructions

all

one one .

, full

the exampl stages instruction

Using clock

the

with thre completes

pipeline is on per

once cy

, , .

cle cycles fully

to

each

though three execute

instruction Thusi

still takes

even .

,

Latency the number of stages

remains . cycle

to

Throughput instruction

increases one per .

However introduces

pipelining

· problems

, :

dependencies

Data depends the

when instruction of

result previous one

on

an a

, .

to

due

hazards branches

Control especially

, .

Pipelining and

when follow

most the

instructions

all

effective

· stages

of

is require

sequence

same

the time

roughly execution

same .

RISC designed

architectures to

explicitly the pipelining which

· of

effectiveness

maximize is

are ,

Why organized five

execution into

instruction exactly stages

is .

The stages

five are :

Fetch

Decode Compute

Execute

Memory Access

back

Write

Each stage by

separated registers

· inter-stage

is operands decode.

read

RA store

RB in

, the

stones

RE output

ALU .

data to to

be

stores

RM written memory .

&Y .

the file

value back

stores to the

be register

to

written

Let's analyze phases

all details

these in : depends

of extensions

The

Extension OPCODE

on

-

immediate va.

- lue

type

R- 32

- type

I-

-

forload

arithmetic

for

orlogi0 alles

for ne

0 s

Or

Fetch

1

. :

The So

Fetch bringing

responsible instruction

for

Stage into

· the the

is :

processor .

The value instruction

PC sent the

to

is memory .

initiated.

read

A is

memory MFC) Completel .

the

The Function

for Memory

waits signal

processor

When asserted

MFC is : loaded (TRI

Instruction

word the Register

into

instruction

The

i is .

' The updated to fixed-length

PC PC instructions

4

ii

. is + assuming .

,

This already

step shows several

· ideas

crucial :

therefore

Instruction fetch

the stage

multi-cycle

be stall.

may

can ,

controlled

PC not

updating explicity automatic

is .

,

and

IR- when

enable PC-enable only

active MFC .

1

are =

Without synchronization

this the fetch

· would instructions

incorrect .

processor

,

Decode

2

2 :

During Decode

the the

stage processor :

,

Interprets opcode

the stored IR .

in

Extracts addresses

register .

from file

Reads the

operands register . 32

-

The file

register

· : s β

read

two (A BI

and

Has ports β

(c)

Has port

write

one 32/32

5-bit addresses 1

Uses allowing registers

32 .

,

fields inside

The the determine

instruction

· :

(Rs Rel

Which registere read

are , (Rol Rel

Which back

register written

is or

Whethe immediate value present

is

an D

. Q

1 REG

1

ㅇ ELK

this

At stage

· : EN

Register copied

value and directly

not need

inter-stage

into registers RB

RA

are .

,

(sign

Immediate high

extended special

extension

values extension

extension zero or

are , ,

,

extension) depending instruction

the type

CALL .

on file

that

This separation subsequent independently

operate register

of

· the

stages

ensures .

3

3 Execute Compute :

In the Execute the used

stage to

· ALU is :

, instructional

Perform logical (R

arithmetic operations type

or .

instructions)

Compute (load

effective addresses store .

instructions)

Perfor (branch

comparisons .

from

inputs to

The

· the ALU come :

operandal

(register

RA and RB immediate

and extended value

RA .

an temporal

the

The the stored into inter-stage

operation register guaranteeing

of

result RE

ALU

· is ,

decoupling

.

In behavior

and by

dictated

compute stage

· entirely

the control

the

component its

ALU is

is

care

, ,

stored

derived opeade

from the the

signals IR

in .

clearly

Two signals visible

of the diagrams

in

groups are

Signals decoding

generated by

directly opcode

the .

Signals analyzed by

from the

and

derived control circuitry

dynamically the output

ALU .

First which

the select operation the addition substrac

performe

signal

ALU-op

· ALU : ,

,

logic

tion operations comparison

or .

,

, generated

The signal field

decoding opcode

by the

directly the instruction

· of currently

is Second

stored B-select fed

which the

the second

value into

MuxB and control

IR

in is

. ,

input

ALU : both

selects operands from

R-type

For instructions RB

MuxB registers

meaning .

come

, , extended

the immediate value

selects

instructions

I-type

For MuxB .

,

ecempstation

distinction

This because reused

be

crucial for

the

it to

allows All

is same

,

Arithmetic instructions

. etocel

(load

tolde

Branch comparisons . which

stored temporally

inter-stage

the

the

The of

output the

register

RE Compute

ALU isolates

is in

· ,

following

from the

stage .

ones

Memory

4

. The when

data

interacting required

stage by

for only

responsible

· with

is

memory memory

load

the all

accessed while

instruction exclusively and store

Memory instructions

by

is o

. ,

there instructions this

through

merely stage

pass .

In this active

the elements

stage

· are :

, (either .

the address

RE computational

output effective

containing ALU result)

an or a

, .

tobe lonls

odetor to

y

contonning written memoey heo

The interfoce

rocessor memone

- . forwoankd

decnides

whicd t

who volue be

till

'

the this

At beginning and

address

of operand

already stable

values

· stage all computation

are :

, the

end

the the

At stage

of

lated stages

carber proc e

in ' ,

.

Write-back stage

the

for warded toward

which

must decide value is .

controlled

entirely decivied

this

Like selection

before by Whose

MaxY

said from

· the

is

is

we op

,

code : (ALU computational

result) for

from used

MuxY instructions

value RZ

0 :

>

= comes .

from for

used load

read

value

MuxY data instructions

1 memory s

= comes .

from address used

value return for instructions

and

MuxY call calls

2 s

= comes .

fundamental

mechanism

This the data

because that path the

"Know instruction

does not

shows

it

is

type behave

datapath

the

that

the logic cly

control

it makes

is rC

car .

volue

The

selected which

stored back file

· t

into the the a

register

RY Wit

written

is in

is

,

Back

Weite

.

5 final

the

This stage the architec

only updates

and

instruction

· the that

stage

execution

of

is

tural the

state of processor .

The elements

Key

· are : file

the

that value

contains selecte