Progettazione e analisi di un convertitore Boost DC/DC per sistemi di veicoli elettrici

Università degli Studi di Napoli

Federico II

Dipartimento di Ingegneria Elettrica e

delle Tecnologie dell’Informazione

Elettrica,

Classe delle Lauree Magistrali in Ingegneria

Classe n. LM-61

Corso di Laurea Magistrale in Ingegneria Elettronica

Tesi di Laurea

Design and Analysis of DC/DC Boost Converter for

Electrical Vehical Systems.

Relatore: Candidato:

Santolo Meo

Ch.mo Prof. Saggese Gerardo

Matr. M61/534

Anno Accademico

2019/2020

Abstract

The thesis presents the analysis and the design of a DC/DC Boost converter used as

first stage of a double stage inverter.

Two Turn-on Snubber solutions are investigated due to the high current slope affecting

the circuit.

Performed simulations show that the applied solutions allow to reduce the electrical

stress of the semiconductor devices without effecting too much the overall efficiency

of the circuit. The lossless solution is more effective than the typical RLD with an

increase of the complexity and costs.

The PCBs are developed considering the budget, the self-soldering without automatic

tools, affecting the choice of the components, and the use of the drilling machine which

does not allow the use of vias.

The developed circuits may be used for further analysis as thermal behaviour of the

semiconductor devices, EMI noise, a better study of the stability; and improvements

as EMI-filters and more efficient snubber circuits.

Keywords

Photovoltaic System, Boost, Snubber, Stability, PCB

ii

Table of Contents

Abstract ................................................................................................................... ii

List of Figures ......................................................................................................... v

List of Symbols ...................................................................................................... ix

1 Introduction ....................................................................................................... 1

1.1 Background ................................................................................................ 1

1.2 Objective and Thesis outline ..................................................................... 4

2 PV Power Systems ............................................................................................ 6

2.1 Classification of PV Solar System ............................................................ 6

2.2 Grid Connected PV System Inverter Topologies .................................... 12

2.2.1 Two-stage Grid Connected PV System............................................ 13

3 DC-DC Boost Converter ................................................................................. 15

3.1 Circuit Description .................................................................................. 15

3.2 Modes of Operation: CCM and DCM ..................................................... 19

3.2.1 Boundary Condition CCM/DCM ..................................................... 24

3.3 Boost Converter Control Loop Analysis ................................................. 26

3.3.1 Right Half-Plane Zero ...................................................................... 29

3.3.2 Voltage Mode Control ...................................................................... 31

3.3.3 Current Mode Control ...................................................................... 33

3.4 Turn-On Snubber ..................................................................................... 38

4 Practical Circuit Design .................................................................................. 44

4.1 Design Parameters ................................................................................... 44

4.2 Components selection .............................................................................. 45

4.2.1 Duty cycle ........................................................................................ 45

4.2.2 Inductor ............................................................................................ 45

iii

4.2.3 MOSFET .......................................................................................... 47

4.2.4 Output Diode .................................................................................... 48

4.2.5 Output Capacitor .............................................................................. 49

4.2.6 Input Capacitor ................................................................................. 51

4.3 Microcontroller ........................................................................................ 51

5 Simulation Results .......................................................................................... 59

6 PCB Design and Guidelines ........................................................................... 72

6.1 Switch Node ............................................................................................ 72

6.2 Guidelines ................................................................................................ 73

6.3 PCB layouts ............................................................................................. 76

7 Conclusion ...................................................................................................... 84

7.1 Conclusion ............................................................................................... 84

7.2 Future Works ........................................................................................... 85

References ............................................................................................................. 86

Appendix A Switch-mode power converter compensation .............................. 90

A.1 Compensation Techniques .......................................................................... 90

A.1.1 Type I error amplifier........................................................................... 91

A.1.2 Type II error amplifier ......................................................................... 93

A.1.3 Type III error amplifier ........................................................................ 94

A.2 Current-mode Boost compensation strategy .............................................. 96

A.2.1 Matlab algorithm .................................................................................. 98

Appendix B Hard switching condition ........................................................... 100

Appendix C RMS Values of Common Boost Waveforms ............................. 103

Appendix D Datasheet components ................................................................ 105

Appendix E Schematics and other simulations .............................................. 110

iv

List of Figures

Figure 1.1 Year of fossil fuel reserves left [3]. ....................................................... 1

Figure 1.2 PV cell, Module and Array [5]. ............................................................. 3

Figure 1.3 Solar PV generation and cumulative capacity [2]. ................................ 4

Figure 2.1 Examples of PV systems [6]. ................................................................. 7

Figure 2.2 Photovoltaic systems components [7]. .................................................. 7

Figure 2.3 Grid connected PV system [10]. ............................................................ 9

Figure 2.4 Off-Grid PV system [9]. ...................................................................... 10

Figure 2.5 Hybrid PV system [9]. ......................................................................... 11

Figure 2.6 Grid-Tied with battery-backup system [9]. ......................................... 11

Figure 2.7 Block diagram of typical grid connected PV system [11]. .................. 12

Figure 2.8 Grid-connected PV system concepts: (a) AC-module PV system, (b)

string inverter system, (c) multi-string inverter system, and (d) central PV inverter

topology [13]. ............................................................................................................. 13

Figure 2.9 Block diagram of two-stage grid-connected PV system [45] . ............ 14

Figure 3.1 Boost circuit [29]. ................................................................................ 16

Figure 3.2 Two configurations of a boost converter: a) On-state and b) Off-state

[46]. ............................................................................................................................ 16

Figure 3.3 Steady state voltage and current waveforms of Boost in CCM [46]. .. 17

Figure 3.4 Effect of parasitic elements on duty cycle [15]. .................................. 19

Figure 3.5 Voltage and current waveforms for Boost converter in CCM [15]. .... 20

Figure 3.6 Boost converter output voltage ripple [15]. ......................................... 21

Figure 3.7 Voltage and current waveforms for a boost converter in DCM [15]. .. 22

Figure 3.8 Inductor voltage for a Boost converter in DCM [15]. ......................... 23

Figure 3.9 Step-up converter at boundary condition of CCM/DCM [15]............. 24

Figure 3.10 Output boundary current as a function of duty cycle D [15]. ............ 24

Figure 3.11 The small-signal equivalent circuit model for boost converter [16]. . 26

Figure 3.12 Resulting circuit after moving the voltage source and the inductor

through the DC transformer [16]. .............................................................................. 27

v

Figure 3.13 Moving voltage source d(s) and the inductor through the DC

transformer [16]. ........................................................................................................ 28

Figure 3.14 The current decreases in the output diode with increasing duty cycle D

[17]. ............................................................................................................................ 30

Figure 3.15 Waveforms of boost converter for a step response in duty cycle [17].

................................................................................................................................... 30

Figure 3.16 Boost converter with Voltage Mode Control [18]. ............................ 31

Figure 3.17 Magnitude and phase curves, two-pole response, for several values of

Q [16]. ........................................................................................................................ 32

Figure 3.18 Control-to-Output Transfer function with the given parameters [47].

................................................................................................................................... 33

Figure 3.19 Control-to-Output Transfer Function with CMC [22]. ...................... 33

Figure 3.20 a) Return of inductor current at its steady state condition b)

Subharmonic oscillation waveform in CCM [48]. ..................................................... 34

Figure 3.21 a) Block diagram of the slope compensation technique, b) PMW

Waveforms with Compensation Ramp [18]. ............................................................. 35

Figure 3.22 RLD snubber in boost converter. ....................................................... 39

Figure 3.23 Effect of the snubber inductance value on the switch turn-on [46]. .. 39

Figure 3.24 The lossless turn-on snubber implemented in a Boost converter. ..... 41

Figure 3.25 Basic waveforms of the lossless snubber of Fig. 3.24 [28]. .............. 42

Figure 4.1 Inductance value function of the current [30]...................................... 47

Figure 4.2 Functional Block Diagram of LM5022-Q1 [39]. ................................ 52

Figure 4.3 Typical Application and components configuration [39]. ................... 52

Figure 4.4 Power stage open loop frequency response and gain and phase margin.

................................................................................................................................... 55

Figure 4.5 Error amplifier: Gain and phase plot. .................................................. 56

Figure 4.6 Bode Plots of the total control loop transfer function.......................... 57

Figure 4.7 Gain and Phase margin of the total control transfer function. ............. 57

Figure 5.1 Boost with ideal switches. ................................................................... 59

Figure 5.2 Ideal Boost waveform. ......................................................................... 59

Figure 5.3 Output waveforms of Ideal Boost. ....................................................... 60

Figure 5.4 Real semiconductor devices. ............................................................... 60

vi

Figure 5.5 Boost waveforms with real components. ............................................. 61

Figure 5.6 Peak to Peak current of MOSFET (blue) and Diode (red) during the

switch turn-on. ........................................................................................................... 62

Figure 5.7 RLD snubber circuit. ........................................................................... 63

Figure 5.8 RLD snubber waveforms. .................................................................... 63

Figure 5.9 RLD snubber effect on the peak current of MOSFET (blue) and diode

(red). ........................................................................................................................... 64

Figure 5.10 Lossless snubber in a boost converter. .............................................. 65

Figure 5.11 Lossless waveforms. .......................................................................... 65

Figure 5.12 External power supply. ...................................................................... 67

Figure 5.13 Oscillation of the output voltage in an unstable converter. ............... 67

Figure 5.14 Boost waveform with RLD solution and IC. ..................................... 68

Figure 5.15 Focus on main waveforms of RLD solution. ..................................... 69

Figure 5.16 Boost with lossless snubber and IC. .................................................. 69

Figure 5.17 Focus on main waveform of the lossless solution. ............................ 70

Figure 5.18 Inrush current: approximation (red) and simulative (blue)................ 71

Figure 6.1 Boost current loops: current paths during MOSFET on-time (red) and

current path during the off-time (blue) [39]. .............................................................. 72

Figure 6.2 Trace Width calculator based on IPC-2221 standard [40]. .................. 75

Figure 6.3 Top layer of the Boost-RLD Board. .................................................... 79

Figure 6.4 Bottom layer of the Boost-RLD Board. ............................................... 79

Figure 6.5 Top layer of the Boost-Lossless Board. ............................................... 80

Figure 6.6 Bottom layer of the Boost-Lossless Board. ......................................... 80

Figure 6.7 3D Board of Boost-RLD. ..................................................................... 82

Figure 6.8 3D Board of the Boost-Lossless. ......................................................... 83

Figure A.1 Type I error amplifier compensation [22]........................................... 91

Figure A.2 Type I error amplifier compensation [22]........................................... 92

Figure A.3 Type II error-amplifier compensation [43]. ........................................ 93

Figure A.4 Frequency response for a Type II error amplifier [43]. ...................... 94

Figure A.5 Type III error-amplifier compensation [43]........................................ 94

Figure A.6 Frequency response of Type III compensation [43]. .......................... 95

Figure A.7 Power stage and Error Amplifier model [44]. .................................... 96

vii

Figure B.1 Power circuit topologies with common network highlighted: a) Buck, b)

Boost and c) Buck-Boost [26]. ................................................................................ 100

Figure B.2 Switching behaviour of a boost converter :a)without parasitic effect, b)

with parasitic effects [24]. ....................................................................................... 101

Figure B.3 Operating point movement or trajectory of the switch during turn-on and

turn-off [24]. ............................................................................................................ 101

Figure D.1 a) Gate charge vs gate-source voltage, b) Capacitance variations [31].

................................................................................................................................. 105

Figure D.2 Forward voltage drop vs Forward current, b) Reverse recovery charges

vs current slope [33]. ............................................................................................... 106

Ω.

Figure E.1 Influence of gate resistance on turn-on of the MOSFET: 5 (green),

Ω (red), 15 Ω (blue) and 20 Ω (purple).

10 ............................................................. 110

Figure E.2 Snubbing inductance effect on the reverse recovery current of the output

diode: 500 nH (gree), 700 nH (red) and 1 uH (blue). .............................................. 111

Ω

Figure E.3 Voltage spikes of the snubbing resistance across the MOSFET: 5

Ω Ω Ω

(green), 10 (red), 15 (blue) and 50 (violet). ................................................. 111

Figure E.4 Snubbing Capacitance effect: 100pF (blue) 700pF (violet) and 10nF

(red). ......................................................................................................................... 112

Figure E.5 RLD schematic with external power supply. .................................... 113

Figure E.6 Lossless schematic with external power supply. ............................... 114

viii

List of Symbols

Frequently used signals and parameters are presented with name and description in the

list below. Signals and parameter that only appear in one of the chapters are not

included in the list. Signals are often divided into a dc part and ac part. The ac part is

denoted by using lower-case letters and listed below, while the dc part is denoted by

using capital letters. The name of signals is reported in the subscript part. A measure

different from average one, it is indicated in the subscript part too, such as root mean

square or maximum value (I or I ).

L,RMS L,MAX

Name Description

‖()‖ Magnitude

∠G(w) Phase

C Capacitor

C Input Capacitor

in

CMC Current Mode Control

C Output Capacitor

O

C Snubbing Capacitance

s

D Duty cycle

D’ 1-D

DCR DC Inductor resistance

D