FPGA implementation of real time algorithms for radar data preprocessing

NATO-CMRE MRN

been made using the RF unit. The user registers parameters are the same used in the

previous test, in the case of mean remover bypassing and in the case of mean remover enabling. The

following parameters are set in the firmware for the board and for the RF module :

X6-400m Parameters : Parameter Value

Bandwidth 300 MHz

PRF 5 KHz

Chirp samples 2044 71

S ampling frequency 10 MHz

Clock frequency 800 MHz

5.11 X6-400m firmware parameters.

RF Parameters : Parameter Value

IF attenuation 0 dB

5.12 RF module firmware parameter.

Below there is the plot of test made with the mean remover bypassed, so the signal is as the RF sends it into

the FPGA :

Amplitude Samples(k)

5.13 FPGA Output SAR signal time evolution plot, acquired with mean remover bypassed. 72

The chirp appear like the one shown in the first chapters, its first samples are included in a big range of

values due to the peaks which affect the signal dynamics.

The mean remover has been enabled to verify its functionality with the SAR input signal and the outcome

can be seen in the following picture :

Amplitude Samples(k)

5.14 FPGA Output SAR signal time evolution plot, acquired with mean remover enabled.

It is visible that the resulting signal very different from the one in the previous plot, the big peaks in the first

samples of the chirp are removed. The dynamics is lower the original signal’s one, and apparently there is

no loss of information. This result can be the starting point of further developments which aim to the data

rate increasing and the reduction of the amount of data to be processed by high level software, there would

be a consistent processing time optimization and also a discrete storing resource saving. These

improvements are part of a good real-time system requirements.

Xilinx design summary 73

Here is reported the final summary generated by ISE Design suite after the generation of the programming

file. This report notify important data such as chip area occupancy, clock and timing situation, not matched

constraint with possible associated issues, performance evaluation and overall project status.

x6_400m_top Project Status (02/20/2015 - 00:42:43)

Project File: x6_400m.xise Parser Errors: No Errors

Module x6_400m_top Implementation State: Placed and Routed

Errors:

Target xc6vsx315t- 1ff1156 No Errors

Device: Warnings:

Product ISE 14.2 16634 Warnings (6 new)

Version: Routing Results:

Design Goal: Balanced All Signals Completely Routed

Timing X

Design Xilinx Default 4 Failing Constraints

Constraints:

Strategy: (unlocked) Final Timing

Environment: System Settings 1980591 (Timing Report)

Score:

Device Utilization Summary [

Slice Logic Utilization Used Available Utilization

Number of Slice Registers 41,065 393,600

Number used as Flip Flops 40,888

Number used as Latches 153

Number used as Latch- thrus 0

Number used as AND/OR logics 24

Number of Slice LUTs 35,466 196,800

Number used as logic 28,014 196,800

Number using O6 output only 18,327

Number using O5 output only 1,279 74

Number using O5 and O6 8,408

Number used as ROM 0

Number used as Memory 5,158 81,440

Number used as Dual Port RAM 4,202

Number using O6 output only 2,622

Number using O5 output only 56

Number using O5 and O6 1,524

Number used as Single Port RAM 0

Number used as Shift Register 956

Number using O6 output only 919

Number using O5 output only 2

Number using O5 and O6 35

Number used exclusively as route- thrus 2,294

Number with same- slice register load 2,198

Number with same- slice carry load 94

Number with other load 2

Number of occupied Slices 15,092 49,200

Number of LUT Flip Flop pairs used 47,447

Number with an unused Flip Flop 12,837 47,447

Number with an unused LUT 11,981 47,447

Number of fully used LUT- FF pairs 22,629 47,447

Number of unique control sets 1,622

Number of slice 6,290 393,600 1%

register sites lost to

l

Number of bonded IOBs 488 600

Number of LOCed IOBs 488 488

IOB Flip Flops 201

IOB Master Pads 39

IOB Slave Pads 39

Number of bonded IPADs 18

Number of LOCed IPADs 2 18

Number of bonded OPADs 16

Number of RAMB36E1/FIFO36E1s 211 704 75

Number using RAMB36E1 only 190

Number using FIFO36E1 only 21

Number of RAMB18E1/FIFO18E1s 43 1,408

Number using RAMB18E1 only 43

Number using FIFO18E1 only 0

Number of BUFG/BUFGCTRLs 19 32

Number used as BUFGs 18

Number used as BUFGCTRLs 1

Number of ILOGICE1/ISERDESE1s 249 720

Number used as ILOGICE1s 115

Number used as ISERDESE1s 134

Number of OLOGICE1/OSERDESE1s 373 720

Number used as OLOGICE1s 98

Number used as OSERDESE1s 275

Number of BSCANs 0 4

Number of BUFHCEs 0 144

According to the previous tab, an average of the used available resources of the FPGA has been made. The

outcome is that for this project version implementation about the 33% of the area has been used. The result

shows how the chip is used according to the project complexity and features. 76

Performance Summary

1980591 (Setup: 1611547, Hold: 369044, Component

Final Pinout Pinout

Timing Data: Report

Switching

Score: Clock

Routing Results: All Signals Completely Routed Clock Data: Report

Timing X 4 Failing Constraints

Constrain

ts: Failing Constraints Best Case Timing Timing

Worst Case

Constraint Check Achievable Errors Score

Slack

*TS_REF_ADC_CL= 1523624

931

- 4.982ns

SETUP 9.982ns

P ERIOD TIMEGRP 369044

255

- 3.117ns

HOLD

"TNM_REF_ADC_CLK

" 5 ns HIGH 50% -1.346ns

SETUP

* T S_inst_crm_inst_sys_clk_clkout0 = PERIOD 66630

348

5.192ns

T IMEGRP "inst_crm_inst_sys_clk_clkout0" HOLD 0.015ns 0

0

T S_sys_clk_i / 1.3 HIGH 50%

* T S_ADC_CLK = PERIOD T IMEGRP - 1.018ns 6.018ns

"T NM_ADC_CLK" 5 ns HIGH 50% 21284

56

SETUP - 0.023ns 0

0

HOLD

* T S_inst_afe_top_inst_dac_intf_dac_clk_bufr = 1 9

- 0.009ns 4.009ns

PERIOD T IMEGRP SETUP 0

0

"inst_afe_top_inst_dac_intf_dac_clk_bufr" - 0.064ns

HOLD

T S_DAC_CLK_IN * 2 HIGH 50%

Timing constraints provide all design requirements to the implementation tools. This also implies that all

paths are covered by the appropriate constraint. the data must be stable prior to the clock edge (setup

time, Tsu) and maintained after the same clock edge (hold time, Th). Not meeting the constraint means

there could be clock skew problems along the logic. In an ideal design, there will be minimal clock skew (all

worst case

flip-flops see the clock edge at the same time, within a few hundred picoseconds). The columns

timing score

indicates the worst values of setup and hold delays for each constraint violation, the column

best case achievable

indicates the number of components interested by the violations and the column

indicates the maximum frequency the indicated clock signal can run. For instance the best case achievable

TS_REF_ADC_CL 9.982 ns

of is which means that it can run just a little over 100 MHz of frequency. 77

Chapter 6

Future Developments and applications

6.1 Implementation of a data representation range reduction

The previous implementations, in particular Mean Removal implementation, aim to reduce the data

representation range to get more samples together in the same word with a gain of speed up in the data

Data Reduction.

reading. The pattern that could be potentially used in this final step has been called It puts

the samples in a new order, so in the end it creates a new data packet. Here follows a possible

implementation of the Data Reduction which has been tested only using RTL simulation.

ii_data_reductor_b8,

The component created has been called and its main function is to take the incoming

14-bit wide samples, reduce them to 8-bit wide samples and putting them on a 32 bit bus together grouped

by 4 . The component would be placed after the mean removal block and the decimation block. Bypass of

the pattern would also be possible. 6.0 Data redactor component block. 78

Here follows the pinout of the component with the related VHDL code and a brief explanation of the

behavioral mechanism.

Pinout

input clk

• : 1 bit, clock signal

rst

• : 1 bit, pipeline reset signal

data_frame_in

• : 1 bit, signal of input data frame, active high

data_vld_in

• : 1 bit, input data valid signal, active high

data_frame_out

• : 1 bit, signal of output data frame, active high

data_in :

• 28 bit, input data bus

data_vld_out :

• 1 bit, output data valid signal, active high

bypass : ii_data_reductor_b8

• 1 bit, signal of bypass, active high

output data_out :

• 32 bit, out data bus.

The data reduction pattern is based on using two busses : the original input one and a 1-clock cycle delayed

toggle

version of the previous one. A signal is generated, its value is changed from high to low or viceversa

clk. toggle

at every rising edge of Only when is high the samples are put on the output bus. The two samples

data_out

of the delayed bus are truncated from the 8th bit to the 14th bit and put on the first half of (from

th and from the 9th to the 16th) because they are the two oldest samples following the input

the 1st to the 8 data_in

order, same thing is done with the input bus with the difference that this time samples are going to

data_out

be assigned to the second half of (from the 17th to the 24th and from the 25th to the 32nd)

because they are the two newest samples with respect to the input order.

process(clk,rst)

begin

if(rst = '1')then

data_frame_in_d <='0';

data_frame_send_d <= '0';

elsif(rising_edge(clk))then

data_frame_in_d <= data_frame_in;

data_frame_send_d <= data_frame_send;

toggle_del <= toggle;

end if;

end process;

process(clk,rst)

begin

if(rst = '1')then

toggle <= '0';

data_in_del <= (others => '0');

elsif(rising_edge(clk) and data_frame_in = '1')then

if(data_vld_in ='1')then 79

toggle <= not toggle ;

data_in_del <= data_in;

end if;

end if;

end process; data_frame_in_d, data_frame_send_d

In the code slice above there is the process for the generation of

toggle_d data_frame_in, data_frame_send

and which are the one – clock cycle delayed versions of and

toggle. toggle

The following process is for the signal generation and the delayed input bus generation

data_in_del. data_frame_in,

All is ruled by the clock signal and by value of when it is high means that there

is available data on the input bus. Both the processes are sensible to the clock signal and the reset signal to

rst

set default value everytime is to high logical level.

data_frame_out <= data_frame_send;

process(clk,rst)

begin

if(