Embedded Systems - Advanced Operating Systems - Appunti

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The followings are the design phases when the PCB is selected as an

architectural solution:

1. Selection of components based on schematics;

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2. Manufacturing of the support for the chosen components. It is the

PCB itself made of three different materials: a conductor (e.g.: cop-

per), an insulator to separate the tracks and provide a support for the

components (e.g.: fiberglass epoxy resin) and a glue, typically called

pre-preg to keep the different layers together. The main phases of the

PCB production are:

• Preparation of the dielectric supports;

• Conductive tracks manufacturing;

• Assembly of the insulating layers that are alternated with pre-preg

layers;

• Drilling the board to create through-via, blind-via and buried-via

holes;

• Manufacturing of the external layers of the board using conductive

materials;

• Finishing of the board with a thin insulating external layer.

3. Board testing to check the interconnections. Sometimes the boundary

scan technique is used: several flip-flops and multiplexers are connected

together in a chain in order to provide and read data with respect to a

particular pin of the system;

4. The components are finally mounted and soldered on the printed circuit

board.

Some remarkable facts to take into account during the PCB design are:

• The more the pins of a component, the higher the complexity of the

board;

• Signals with very high bandwidth should not be brought on the PCB,

but it is more advisable keep the communicating sections inside a single

chip;

• The latency and the delay of the signals running on the PCB tracks

can be very high.

2.2 System-on-Chip

With this term we identify a complete system with all its parts integrated

on a single silicon chip. Some of them cannot be integrated due to their

mechanical characteristics, therefore a SoC is a device carrying out the main

functionality of a system. Some relevant features are being analyzed:

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• integrating most of the functionality on a single mi-

System cost:

crochip, the final board is smaller and less complex while the total cost

will be affordable if the volumes are significant.

• as far as the size is concerned, signal lines are not used

Performance:

to be found ensuring signal integrity.

• nowadays the complexity of the systems requires a

Input/Output:

large number of input and output signals. If they are gathered on

different chips, this could lead to packages characterized by a huge

number of pins, a bigger size and a higher cost.

• this is a very relevant aspect because we want to protect

Security:

our product from reverse engineering and competitors. Moreover, if

the system elaborates sensitive data, it is necessary to protect them

from unauthorized accesses.

A System-on-Chip is always made up of a minimum set of functional blocks:

• One or more processors such as microcontrollers, general purpose, net-

work and digital signal processors;

• Different kinds of memories (e.g.: RAM, ROM, EPROM, EEPROM,

Flash);

• Some specific and application-relevant digital blocks;

• Other types of blocks such as timer blocks, power supply blocks and

some analog/digital interfaces.

As far as SoC are concerned, two different classes could be recognized: MP-

SoC, that are multiprocessing systems, and NoC, that are systems charac-

terized by a peculiar communication infrastructure instead of a typical bus

architecture. Moreover, in the latter, data are exchanged as packets.

2.2.1 Dark Silicon

The number of transistors that are integrated on a chip is very high and it is

increasing rapidly over the years. On the other hand, the power consumption

per transistor has not dropped at a corresponding rate. A huge problems

pops up: due to a real physical limit and heat generation, there is no way to

have all the transistors on a chip turned on at the same time.

The name "dark silicon" comes from that silicon area of the chip that is

switched off. 7

2.3 Distributed Systems

A Distributed System is a system in which computing and storing are not

carried out in the same place, but in different systems properly connected.

In order to consider an embedded system distributed, it has to be made up

of several subsystems which exchange a huge quantity of data.

We can distinguish between two main classes with respect to this kind

of systems on the basis of the connection type: wired systems, which are

connected by wires, and wireless systems, which are connected by a wireless

communication.

2.3.1 Wireless sensor network

A wireless sensor network is characterized by a set of nodes distributed in

a wide area. Each node has a microprocessor, a memory, a transceiver, an

antenna, a battery and sensors and cooperates with the others in order to

have the surrounded environment monitored. Some relevant features of this

kind of systems are:

• nodes heterogeneity;

• communication infrastructure and nodes failure;

• long-life batteries;

• nodes portability.

The main actors of the systems are the nodes together with a gateway, a host

and a private communication channel. The nodes can be gathered in different

groups and each group elects a master node. Afterwards the master-nodes

create a higher level communication structure to deliver information to the

gateway.

2.4 Development platforms

A great variety of development platform is available on the market. The

most significant are the following:

• they are broadly used when the production volumes are con-

ASICs:

siderable. They assure the best performance and the lowest power

consumption. Moreover they are very application specific and their

cost is really high. 8

• they are a smaller and static version of an ASIC

Microcontrollers:

integrating different components, such as memories and ADC/DAC,

without the possibility to expand their functionality but outside the

IC.

• they are the perfect platform to assure flexibility and small

FPGAs:

time to market, but the production volumes should not be enormous.

They are fully programmable devices which can count on specialized

functionality and software flexibility.

• all the stuff is integrated in a single chip with more than one

SoC:

processor, memory, controllers... The volumes to afford such a choice

are not always easy to achieve.

2.5 The Multi-Core Revolution

In the past we used to increase the frequency of the processor in order to

get better performances, but this led to some thermal and power issues.

Afterwards a new approach came up : more and less complex cores were

wrapped up inside a single microprocessors and this allowed the parallel

hardware execution of the applications. Nowadays this is the philosophy

with respect to designing and building processors.

The so called performance gap is a common problem: it is the difference

between the expected performance and the one we actually get. In fact the

higher computation power has to be exploited properly even by using better

software to avoid a totally waste of energy.

What the users want is more performance and energy efficiency, therefore

it is relevant to make changes to and improve the current technology. In

order to do that the CMOS technology has experienced a deep evolution and

the trend is to reduce the size of the transistors, but the power dissipation

per cm2 has been increased leading to thermal and cooling issues. On one

hand smaller transistors let to create more powerful chips with many cores,

on the other hand this leads to a higher complexity and more escaped bugs.

The fact is that the technology is scaling down, but we do not want to lose

reliability in order to make electronics devices successful.

When we talk about reliability it is important to point out the difference

between two kinds of faults: an Hard Fault happens when the device breaks

down due to an improper use and it experiences an irreversible physical

change, an Escaped Bug is a design error which makes the device not com-

pliant with the specifications. We are able to verify and validate our design

through formal methods as well as RTL (Register Transfer Level) simulation

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used to create a high level representation of the circuit in hardware descrip-

tion languages like Verilog and VHDL.

2.5.1 On-chip interconnect architecture

As the trend is to split the complexity of our devices to reduce the power

consumption and to simplify the hardware design raising performances and

creating explicit parallelism, the interconnections, for example among some

cores, are more and more important. There are different types of architec-

tures:

• it is not scalable because the link count grows as

Point to point:

on the other hand we can count on a full throughput between

n·(n−1),

masters and slaves. A single faulty link prevents the communication;

• the bus is a single shared communication medium, a synchroniza-

Bus:

tion and serialization point which requires an arbiter to be properly

used by all the connected devices. Any attached device can observe

the data on the bus. Contention grows with the number of attached

masters onto the bus, furthermore it is a single point of failure;

• it is a multi-bus architecture which requires an arbiter.

Crossbar:

There are multiple paths to reach the same resource, moreover it has

better performance with higher power consumption and area;

• this kind of interconnect is based on the network theory to bring

NoC:

improvements to bus and crossbar technologies. No assumptions can

be made about the taken path from source to destination since it is

based in coherence protocols. Moreover data are exchanged as packets.

This architecture is fully scalable and reliable.

The interconnect always routes data and instructions as request/reply and

load/store operations.

2.6 On-chip bus

When we have to develop a bus we start from the specification document and

we choose some aspects such as the signals to be implemented, the control

path as an arbiter and the data transfer protocol. Wishbone is a copyright

free bus specification extensively used in open hardware projects.

The bus can manage different signals:

• the address bus routes the destination address provided by the master

and it can be shared with the data bus;

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• the data bus transfers data to/from master and slave during a bus

transaction;

• the control bus carries out the protocol specific signals to handle the

bus transactions (e.g. read/write signals, ack errors, data validity...).

Speaking about the architecture, a tri-state one is mostly used for off-chip

communication because of high delay and high power request while a Mux

and AndOr is more efficient. There are different components that interact

with the bus:

• the master is a module that can trigger a bus