Note per laboratorio di Fundamentals of electrical systems

Just a remark: since TL082 is low bias input current device (some pA), the main

contribution of the offset parameters on the output is mainly due to V_off.

Then, for EACH of the other circuits, you need to evaluate:

1. The OUTPUT VOLTAGE OFFSET, that is the contribution of all the offset of the stages (if

more stages are present), simply grounding the input and measure the output.

2. The bandwidth limit of that circuit (it depends on gain..)

3. The maximum output current with which that circuit can drive the load.

3. How to calculate the output current limit?

resistor…

Think about the load

4. What do you mean with I/O characteristics?

Drawing the I/O characteristics means to plot the output quantity (y-axis) - to be

measured - wrt the input quantity - known - that you use to feed the circuit (x-axis).

For example: for the Voltage follower both the output and input quantity are voltages,

while in the transimpedance the output is a voltage and the input is a current, etc..

Basically, you give a certain input (Vin=3V or Iin=3mA), then you measure the output

value (Vout or Iout) corresponding to that value of the input and plot them. You should

vary the input since the output saturates..

5. Can the saturation of the opamp be asymmetric?

Yes, it can. This is due to the intrinsic asymmetric structure of the operational amplifier.

Let’s take as an example a voltage follower feeds by a ±15V power supply. When

applying a sinusoidal 28V peak to peak input voltage, it can happen, for example, that at

14V the output starts its “positive” saturation and saturates at 13.8V. While at -14V the

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output voltage it is not saturated anymore. Thus, we’ll increase the peak to peak voltage

at 29V and we notice that at -14.3V, the output starts its “negative” saturation. This is

just an example to let you understand that this kind of behaviour is possible, or better, it

will (almost) always happens.

6. Transconductance amplifier design.

It is worth to use a non-inverting amplifier where as load resistor is considered the one

on…

7. How can I measure a current flowing in 1kΩ resistor, giving as input voltage Vin=V2-V3 to

the IA? For example, you can simply create an input circuit with an input voltage and two series

resistors. Then, as input voltage for the IA, just take the voltage drop on one of the two

resistors… 1kΩ

Remember, that resistor has to be a resistor. 7

Lab03 FAQ ES4M.

In this lab activity you are allowed to use the E6 series of capacitors having a 20% tolerance

0. A brief comments about requirements.

Since the requirements seems to be very restrictive, try to do the best you can! The

most important thing is to well explain the choices made in your report. There is not a

unique way to proceed that is better than others since you do not know the application

of this filter. Choose a good compromise in your design and describe it accurately.

Some tips that we can give are:

1. You could use a 10th order filter.

2. Try to use Chebyshev 1 dB.

3. Try to increase a little bit the stopband limit frequency.

4. If the peak is too high, try to reduce the gain of the first stage.

Moreover, the design has to be done taking into account ideal values for the resistors

and capacitors. Then, you need to verify the behaviour of the entire filter with the true

values (series E12 for resistors and E6 for the capacitors).

1. Which kind of cells do I have to use for the design?

You are allowed to use only Multiple Feedback stages.

2. Which amount of ripple do I have to choose in the passband region?

Well, you should think about the fact that components (resistors, capacitors) have

tolerances. Furthermore, you only have specific values for resistors. (Even if you are only

simulating the circuit) I suggest to stay with the minimum ripple possible and then verify,

if the mask parameters limit are respected. Of course, try always to minimize stages.

3. Which values for capacitors do I have to choose?

Since you are just simulating the circuit, the values that you choose for the capacitors is

not a crucial task. The aim of the lab session is to design something implementable on a

real board. In this sense, capacitors play a fundamental role. Considering that the input

capacitances of TL082 are about few pF (see datasheet), the values for the capacitors

have to be at least hundreds of pF. Furthermore, the layout of the breadboard has a

capacitive influence on the circuit. The suggestion is to start designing the first cell with

capacitance on the order of some nF. The more you increase values for resistors, the less

will be the calculated values for capacitors.

4. Tips for designing and tune each cell.

Design - A possible way to design the MF cell is to start from capacitors, since you have

less values available than resistors (E6 series vs E12 series). Try to choose a “good” value

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for capacitor C4 (some nF) and then choose a value for C5 big enough (hundreds of pF)

such that is greater than layout and input capacitances (see FAQ 3 in Lab03). Then, find

the values for the resistors to be implemented. Pay attention to not choose C5 too big

because then R2 becomes complex.

Tuning - Frequency f0 with R3, Q with R1 that does not compromise the frequency, and

then the DC-gain with R2. Then, repeat it since by varying R2 both the frequency and the

quality factor change (but not so much).

5. Should I use the wizard or the table for designing the filter?

You can both use the wizard or the table. It’s up to you. Just remember that tables are

normalized and expressed in decades and so the value corresponds to the cutting

frequency. 9

Lab04 FAQ ES4M.

0. A brief comments about requirements.

In this lab, you have to design the following circuits:

1) Single wave rectifier (1 diode)

2) Ideal diode (2 diode)

3) Double wave rectifier with and without capacitor

4) Shmitt trigger with a certain thresholds

5) Astable multivibrator with a certain frequency

6) Wien oscillator at a certain frequency, Bang-Bang configuration

For all the aforementioned circuits, it is recommended to carry out the simulation (and so

calculate all the values of required resistances, capacitor etc to produce the required frequency)

beforehand.

In the report, all the circuits must have a transfer function present. 10

Lab05 FAQ ES4M.

1. Design tips.

As written in the lab4.pdf, during the design procedure you should take into account the

≈

maximum power dissipation of the resistors ( 0.25 W), but also the maximum output

current of the opamp used (remember that you have already calculated this value in the

Lab0102). In particular, consider that when the input of the D/A converter is “1111”,

then in the feedback resistor will flow a current almost equal to 2I, that has to be less

than the maximum output current the opamp can accept.

In the same way, when the input of the D/A converter is 0001, in the feedback resistor

will flow a current equal to I/8, that has to be greater than the input bias current of the

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opamp used ( hundreds of nA).

Finally, since you have to implement the ladder network designed with the current

switches also with the counter based DAC, you have to take into account the output

impedance of the counter’s pins, making a suitable experiment ( use the concept of

voltage divider ).

2. Practical resistor implementation (in a real circuit).

Once you define the resistor R to be used belonging to the E12 series, you can put two

of them in series to obtain the 2R values (since 2R is not present in E12 series).

3. What is the purpose of the DEMO part?

The aim of the DEMO part is to change a lot del values of the ladder network such that

big non linear differential errors are generated, causing a non monotonous behaviour in

the DAC characteristic. 11

4. Comparison D/A converter with current SW and voltage SW (no counter).

The most striking feature here is the fact that in the voltage switches configuration the

current flowing in the branches is not a fraction of 2^n as in the current switches...why?

Even if this happens, there are no differences at all between the two implementation

since the reciprocity principle guarantees it. Furthermore, the behaviour is very close to

the ideal one since the resistance of the single switch is negligible.

5. What behaviour do I have to consider as ideal?

The ideal characteristic is modeled by the line that goes from the point (D=0000,Va=0V)

to the point (D=1111, Va=+5V), where D is the digital value and Va the analog value. 12

Lab06 FAQ ES4M.

1. How do we calculate the error due to the output impedance of the counter?

The out impedance of the counter is summed to the series resistors of the ladder

…?

network, thus it alters the 2R values causing an error of Anyway, if the ladder

network is designed with values of R significantly big, the error due to the out

impedance of the counter can be neglected.

2. How do we create a missing code error?

Usually it is needed to vary a lot the values of R such that not monotonous errors occur

in the D/A characteristic. A not monotonous error in the DAC, implies a missing code

generation.

I suggest to generate a not monotonous error right where you want, for example when

passing from 0111 to 1000. This can be done increasing a little bit the value of the

resistor on the MSB branch (let’s call this “new” resistor R_MSB), such that the current

flowing in that branch will be less than expected when the pin Q4 is activated (1000)

and, as a consequence, a smaller analog value will be produced as output of the DAC.

Tuning R_MSB, you can obtain an analog value associated to D=1000 smaller than the

one converted when D=0111.

3. My counter starts count from 0 to 15 when the input signal is close to 5V or/and 0V.

Suppose that the dynamic of your ADC is 0V,+5V (very accurate). Let’s suppose you want

to convert an analog value equal to 2V and that the DAC gives 1.8V when D=0011 and

2.2V when D=0100. The tracking ADC will give as output a value that oscillates between

0011 and 0100. Now consider the case we want our ADC to convert the 0V value.

Probably the DAC you have designed when D=0000 it gives as output some millivolts. So,

when we feed the ADC with a 0V value, then the comparator compares some millivolts

with 0V and since some millivolts are greater than 0V, the counter counts down ->

D=1111. The value associated to D=1111 is again greater than 0V and the counter counts

etc…

down again, For the +5V the same reasoning can be applied.

4. Conversion delay

The conversion delay is the time needed by the converter to convert the maximum

analog signal convertible that, in this case, is a signal passing from 0V to +5V

instantaneously. It is needed time to do this since the DAC block has to pass from

D=0000 to D=1111. So you need to feed your circuit with a Va equal to a square wave

that goes from almost 0V to almost 5V, depending on the dynamic of the ADC you have