Unwind di Analogue Integrated Circuit Design - 4 di 5

Let’s put now everything together

l 204.103203 8ms 8ms13 VoRicRicii iiTo obtain the output voltage vo it must be firstly evaluated the current i3:Imsis _iie dieRic Ric203 203I lRic Ric8ms203 203Ims Ims tict.liV is Ric Ric RicIRos204 204IRicGm 203 t VicIml'ieRic Ric 20h204 IÀ 2205tfmsR.ec tfmsR.ecI i20 203Im Vice'io Imi 2205 iImiti liVia Ric8ms 2020hfinRic 22051 Gm1 220520 i tt gin2205 2205It Io20 2047mi 7miNoVic temoogni ogniVieGm Gm2205 2205So the CMRR is: RagniCMDR 22058msAdamotemof O fm.roAdamo2,49ms8mi 2µF 2,99ms8mi9mi I2oz MplIo 13 5111ID 19,8111Mnl74703 IDIss IbiIma 2M2 IDVous IeriMPLS 13,5Los IDsUsing these values, the CMRR is: i62dBCM 1RR 103f O

Question 4

Let’s evaluate now the input common mode range:DD M5 stays in saturation as long as: Vd5<Vdd-Vov5.145 VIE KipVIC VousVipVai Voti1Vic mi VTNtvovs.msOVM1 stays in saturation as long as: Vd1<Vgs1-Vtp=-Vov1iVipVas Vos Vorvi trovi VonVipVousTnt c VVIC 16KIN tv 0Vous1The last result corresponds to the lower limit of the input voltage.The upper limit of the input voltage is given by: Vor ViKcVIE VICKip VigVan 0,499VipVousVipVai VousVonSo the input common mode voltage must satisfy the following condition:Vthe16V 0,4990

Problem 2

Consider the telescopic cascode OTA depicted in the figure below. Assuming that the bias voltages V ,CPV and the input common-mode voltage V are such that the amplifier transistors M -M operate inCN IC 1 9saturation region:

• 1) Determine the bias currents I and I so that the unity gain frequency of the amplifier f = 400 MHzD1 D2 u(assume that the frequency of the OTA non-dominant poles and zeroes is much larger than f and thatuparasistic capacitances are negligible with respect to C );L-M (assuming I = 1.25⋅(I +I )) and re-compute f taking
• 2) Determine the gate width of transistors M 1 9 D9 D1 D2 uinto account the parasitic capacitances;
• 3) Compute the frequency of the dominant pole and the low-frequency differential voltage gain A ;dm0
• 4) Estimate the frequency of the non-dominant pole, keeping in mind that it is associated with nodesX – X’.

Data γ γV = 3.3 V, C = 1 pF, L = L = 400 nm; = g /I = 10 (k = 1, …, 6), = 4 (k = 7, 8, 9).DD L 1-9 k mk Dk k

MOSFET parameters for hand calculationη χ2 2 C = C Ck’ [µA/V ] [V/m] = g /g C [fF/µm ] GS0 GD0 jd/sn/p mb m ox [fF/µm] [fF/µm](*)7nMOSFET 175 0.2 4.6 0.21 0.461.8⋅10 7pMOSFET 60 0.2 4.6 0.21 0.711.25⋅10 ≅ ⋅W, ≅ ⋅W(*) You may use the approximate relation: C C C Cdb jd sb jd

Question 1

The currents Id1 and Id2 must be chosen such that:fu 400MHzWhere fu is the unitary-gain frequency.If the frequency response of the OTA can be approximated by a first order response between 0 and fu, then:E f Imifu Ro ziffiAdamo zqfz.ciAssuming that load capacitance is equal only to CL because load capacitances are all negligible:E leiCi Cit C 8mi 2ITL 2,51mifu Gm fuci21T i8 8mi In 251Mtlo IdaIdi

Question 2

To determine the gate width of the devices, let’s consider: VaVoi Im kmIs µµKimInverting the first equation:IIslW VoiKiWhile inverting the second one:W IniImL LKip KIN ID2Von 2Voir Io8mWUsing the equations, the gates widths are: WaL Sem 83 8È pm2k IsiIda Idle IIscoIdaIdeeID D8aIda I 25 INIsi 8ms i2 Ima 8mg51mi GmaGm t.CO8mg mWs83W4 8µmWs We 28,7km4W8 i i6 WgW 33 MmMm 5

Question 3

Let’s firstly evaluate Adm0: iRoIm RonAdamo Voi GmVod Vor RapviiVid Via E IIviRon 7oz207 Gm's 205205