Unwind di Analogue Integrated Circuit Design - 1 di 5

Lesson #01 lesson #02

Ehi 7 LIDdLets see now basic single-mosfet stages.

Lesson #03

These stages are common source, common gate and common drain stages.

The first stage analysed is the common source (CS) stage. Common source means that the source is common tothe input port and to the output port. The considered circuit is:VbbRa tob ODSG vos

The device must be in the saturation region to act like an amplifier. The voltage “vGS” is the small signalsigapplied to the device and this voltage must be small enough e to let the device remain in saturation region(vds>vgs-Vt>0).

It’s important to know how this elementary circuit works in order to understand how more complex circuitsbased on the interconnection of these elementary circuits work.

Small signal model

In a simplified analysis, the small signal model of the device valid for all frequencies is:is0 itsToTgs Images

The equivalent small signal model of the mosfet is a voltage controlled current source (shortly VCCS). Themodel considers the output resistance “ro” due to the fact that this is a real device where idealities are not valid.

The complet ideal mosfet doesn’t consider “ro”, so the equivalent small signal of a complete ideal mosfet is:ii The drain current is “iD’”, that is the ideal drain current.ig.co OssTgs Images

In this model, if the gate voltage increases, the device generate a greater current, due to the fact that the draincurrent is linearly dependent by the gate voltage.

Considering the starting circuit another time:Vbb isra JoD JoRaTgsODSG Tgs S

Note that the resistor “RD” is between drain contact and mass because at the variation, so when small signal isapplied, the voltage of the supply is constant, so it’s variations are 0. To represent this fact, a mass reference isimpose to the terminals where voltage supply is applied.

Using this last circuit, it can be found the voltage gain: Riardi8miImitasseJor Avo JoReid ReR ee Ugs

The device in particular transforms the voltage variation applied at the gate in a current variation. This currentvariation is transformed in a voltage variation due to the load resistor “RL”.

A more accurate model considers the output resistance “ro”:Odsios To RiTgs 9m95

In this model is evidenced the presence of the ideal model and of the mosfet low frequency model.

In this case, considering the output resistance, the voltage gain becomes:NR iRi Tor iNRIn To0oz TgsIAv Simili

Parasitic components

Let’s consider now the ideal model of the mosfet with all parasitic components:ign riZicos s'g µio ToCab to Zohraririif cos Equal to “ZL’”.

This is the full model of the device. In this case the current “id’” is not the only current that flows through theequivalent load, but there is also the “igd” due to che “Cgd” parasitic component. This current is not negligibleat high frequency. Let’s see where this capacitance is applied:iga Jos ToSegae1Caos golJos Jo

The equivalent model is so:igaCGD io JoÈJI cos

The capacitance “CGD” affects the output voltage so it must be considerate in the calculation of the transferfunction, while the capacitance “CGS” affects only the input impedance so doesn’t appear in the calculations ofthe voltage gain transfer function.

In this last circuit, the output voltage is: Jos JoidZivo igdr.zigmvgs.sc.esr scabziscgar.fmJo Zi Josti i ImCGDGm Zi 5o ImJoAv 5 a 2 ZiOas I t GDs

The definition of “ZL’” is:ri RiZi I eµ Sri CDBse I t

Substituting this expression in “Av(s)”, the result expression is the following:ri scab8ns iIo GmAv Sri CDB5 Ia_ at RiGas I GDt s SRI CDB1 tri scabicom GmSRI CDBI t tsricsbtsric.GSI CDBSRII t scad 8nsri ricom i i SEIImSri sbtc.GSSRI Cod RiCsitI 5it

Substituting “s” with “jw{, the result is: juiced8ns Ri JWi IAviv ie_AvoGm Wze tjwricsbtc.GS JW1i WpRi i8m70 i 8miIm Nila WpaWz 1Avo ee CGDRiCGD spot

Tipically:ri Nzi WpIm

The Bode diagram of the transfer function becomes so:tu inAvo alle20dB Wiz WlogWiWp

The amplification appears only for frequencies below “wT”. Considering what happens for “w” that goes toinfinite, the transfer function becomes:JW1Avotv tv Wp 1in inWzr WzJ W Wi Wp

For increasing frequencies, the output voltage is attenuated in respect of the input voltage variation.

Non idealities

Lets now consider some non idealities about the voltage that drive the circuit:

Now the voltage “vgs” is different by the voltage “vI”. The voltageVbb “vI” sees a voltage divider that creat the voltage “vgs”. Thevoltage divider is composed of the resistance “RI” and the inputRi impedance named “ZGS”.2GsR ioÒ vos

To determine the new voltage gain, lets firstly determine “ZGS”, comsidering the following circuit:igaGD IIs 22 id GsGsR 2 RICostToZIigsÒ vos Cos

Let’s consider in particular a test voltage “vt” applied here and let’s measure the ratio between “vt” and “it”:igsrscosotiigdescado.to