Linee guida SystemVerilog

SystemVerilog RTL Guide (Minimal but Complete)

Integrated from Teacher Slides + Personal Notes

Contents

1 Core HDL Concept (What SV is doing) 3

2 Modules and Ports (The hardware block) 3

2.1 Module syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 Why written like this . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.3 General rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Signals, Types, and Operators (Minimal essentials) 3

3.1 logic, signed, vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.2 Key operator families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Combinational Logic (How to write it correctly) 4

4.1 (A) Continuous assignment: . . . . . . . . . . . . . . . . . . . . . 4

assign . . . . . . . . . . . . . 4

4.2 (B) Procedural combinational block: comb

always

4.3 Why blocking ’=’ in combinational . . . . . . . . . . . . . . . . . . . . . 4

4.4 Critical rule: avoid unintended latches . . . . . . . . . . . . . . . . . . . 4

5 Selection Logic: MUX and DEMUX (and generalization) 5

5.1 2-to-1 MUX (three equivalent styles) . . . . . . . . . . . . . . . . . . . . 5

5.2 Why needs . . . . . . . . . . . . . . . . . . . . . . . . . . 5

case default

5.3 General N-to-1 MUX (example 5-to-1) . . . . . . . . . . . . . . . . . . . 5

5.4 DEMUX (1-to-2 example, general pattern) . . . . . . . . . . . . . . . . . 6

6 XOR/XNOR and Comparators (minimal SV patterns) 6

6.1 XOR / XNOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2 Comparator (1-bit, multi-bit) . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Arithmetic (Two’s complement, minimal SV usage) 6

7.1 Signed arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2 Shifts (cheap multiply/divide by 2) . . . . . . . . . . . . . . . . . . . . . 7

8 Sequential Logic (Flip-flops, Registers) 7

D flip-flop with async active-low reset . . . . . . . . . . . . . 7

8.1 ff

always

8.2 Register (multi-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

8.3 Counters (general sequential pattern) . . . . . . . . . . . . . . . . . . . . 7

9 Latches (only if you really mean it) 8

1

10 FSM (Finite State Machines) – minimal correct template 8

10.1 Moore FSM (output depends only on state) . . . . . . . . . . . . . . . . 8

10.2 Why 3 blocks? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

10.3 Mealy note (output depends on state + inputs) . . . . . . . . . . . . . . 9

11 Memories (SV modeling used in the course) 9

11.1 Packed word memory array (typical FPGA inference) . . . . . . . . . . . 9

12 RAM and ROM (SV implementations) 9

12.1 RAM (Read/Write memory) . . . . . . . . . . . . . . . . . . . . . . . . . 9

12.2 ROM (Read-only memory) . . . . . . . . . . . . . . . . . . . . . . . . . . 10

13 TESTBENCH (DON’T MISS THIS) – complete minimal verification

flow 11

13.1 Golden structure of a testbench . . . . . . . . . . . . . . . . . . . . . . . 11

13.2 Timescale (recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . 11

13.3 TB signals: what type and why . . . . . . . . . . . . . . . . . . . . . . . 11

13.4 DUT instantiation (named connections preferred) . . . . . . . . . . . . . 11

13.5 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

13.6 Reset generator (Power-On Reset) . . . . . . . . . . . . . . . . . . . . . . 12

13.7 Stimuli (directed test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

13.8 Stimuli aligned to clock (best practice for sequential DUTs) . . . . . . . 13

13.9 Monitoring and printing . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

13.10Self-checking (expected vs actual) . . . . . . . . . . . . . . . . . . . . . . 13

13.11Random stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

$stop $finish

13.12Ending simulation: vs . . . . . . . . . . . . . . . . . . . . . 14

13.13Complete minimal TB skeleton (everything together) . . . . . . . . . . . 14

14 Final Rules (Minimal checklist) 15

2

1 Core HDL Concept (What SV is doing)

SystemVerilog (SV) is an HDL: it describes hardware, not software.

• Combinational logic: output depends only on current inputs.

• Sequential logic: output depends on inputs + stored state (memory).

SV code must be written so that a synthesis tool can map it to gates, flip-flops, and

memories.

2 Modules and Ports (The hardware block)

2.1 Module syntax

// A module is a hardware block with ports ( pins ) .

module my_block (

input logic clk ,

input logic rst_n ,

input logic [7:0] a ,

input logic [7:0] b ,

output logic [7:0] y

); // logic here

endmodule

2.2 Why written like this

• defines a synthesizable hardware block.

module ... endmodule:

• direction of physical connections.

input/output:

• bit-width (bus).

[MSB:LSB]:

• recommended SV type (avoids old vs confusion).

logic: wire reg

2.3 General rule

Break complex systems into submodules, then instantiate and connect them (hierarchical

design).

3 Signals, Types, and Operators (Minimal essentials)

3.1 logic, signed, vectors

// Unsigned by default :

logic [7:0] u ;

// Signed two ’ s complement :

logic s