Motorola 68000 - Instruction set

Appunti in inglese di Architetture Sistemi Elaborazione del prof. Mazzocca su Motorola 68000 - Instruction set: ABCD (Add decimal with extend), ADD (Add binary), ADDA (Add address), ADDI (Add immediate), ADDQ (Add quick), ADDX (Add extended), AND logical, ASL, ASR (Arithmetic shift left/right)

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher flaviael di informazioni apprese con la frequenza delle lezioni di Architetture Sistemi Elaborazione e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università Napoli Federico II - Unina o del prof Mazzocca Nicola.
Anteprima Testo:
The 68000's Instruction Set
We have included this appendix to save you the task of having to turn to secondary
material when writing 68000 assembly language programs. Since most programmers are not interested in the encoding of instructions, details of instruction encoding have been omitted (i.e., the actual op-code bit patterns). Applications of some of the instructions have been provided to demonstrate how they can be used in practice. Instructions are listed by mnemonic in alphabetical order. The information provided about each instruction is: its assembler syntax, its attributes (i.e., whether it takes a byte, word, or longword operand), its description in words, the effect its execution has on the condition codes, and the addressing modes it may take. The effect of an instruction on the CCR is specified by the following codes: U The state of the bit is undefined (i.e., its value cannot be predicted) - The bit remains unchanged by the execution of the instruction * The bit is set or cleared according to the outcome of the instruction.
Unless an addressing mode is implicit (e.g., NOP, RESET, RTS, etc.), the legal source and destination addressing modes are specified by their assembly language syntax. The following notation is used to describe the 68000's instruction set. Dn,
Data and address register direct.
Address register indirect.
(An)+, -(An)
Address register indirect with post-incrementing or predecrementing.
(d,An), (d,An,Xi)
Address register indirect with displacement, and address register indirect with indexing and a displacement.
Absolute addressing with a 16-bit or a 32-bit address.
(d,PC), (d,PC,Xi)
Program counter relative addressing with a 16-bit offset, or with an 8-bit offset plus the contents of an index register.
An immediate value (i.e., literal) which may be 16 or 32 bits, depending on the instruction.
The 68000's Instruction Set Two notations are employed for address register indirect addressing. The notation originally used to indicate address register indirect addressing has been superseded. However, the Teesside 68000 simulator supports only the older form. Old notation
Current notation
d(An), d(An,Xi) d(PC), d(PC,Xi)
(d,An), (d,An,Xi) (d,PC), (d,PC,Xi)
Add decimal with extend
[destination]10 ← [source]10 + [destination]10 + [X]
ABCD Dy,Dx ABCD -(Ay),-(Ax)
Size = byte
Add the source operand to the destination operand along with the extend bit, and store the result in the destination location. The addition is performed using BCD arithmetic. The only legal addressing modes are data register direct and memory to memory with address register indirect using pre-decrementing.
The ABCD instruction is used in chain arithmetic to add together strings of BCD digits. Consider the addition of two nine-digit numbers. Note that the strings are stored so that the leastsignificant digit is at the high address.
Trova ripetizioni online e lezioni private