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# SIS Manual

SIS is a tool from University of Berkeley, California, which incorporate a set of Logic Optimization techniques. It has techniques for optimization and implementation of both Combinational Circuits (Boolean Functions) and Sequential Circuits (Finite-state machine). SIS uses special formats for representation... Vedi di più

Esame di Sistemi embedded docente Prof. L. Pomante

Anteprima

### ESTRATTO DOCUMENTO

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If you want to transport files between windows and UNIX, for example descriptions of

circuits you have done, you can use an ftp-software. Start this software from Windows start

Start -> Internetapplikationer -> Ws_ftp -> WS_FTP95 LE

Observe that there are two “Internetapplikationer” and you should choose the lower one to

find this. You should then fill in the box as shown in the figure below but change the stars to

When you’ve done this and click on “OK” you’ll get a window, which shows your windows-

files to the left and unix-files to the right. If you want to copy a file from one system to

another you just mark it and click on the arrow-button in the middle pointing in the direction

in which the copying should be done. - 16 -

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To start “SIS” you should type in the Unix-prompt and then you’ll get in if the

“sis”

settings described in part 3.5 has worked out. To exit “SIS”, write the command quit.

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The “SIS” user-interface is a command-based software. This means that you have a command

prompt in which you have to write commands to make things happen.

The normal backspace and arrow key does not work in SIS. The two following key

combinations could be used for correcting mistakes.

Ctrl – h backspace

Ctrl – w delete last word

There is not much help included in the SIS software but you can at least get a list of available

## KHOS.

commands by giving command

If you read in a file that have some errors in the format SIS may get into a state that makes it

behave strange. In this case quit SIS and start it again. There could be other similar strange

behavior by other mistake commands.

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Here follows a list with some Unix-commands. Observe that Unix is sensitive to if you use

capital letters or small letters.

UNIX-command Explanation or corresponding DOS-

command

ls dir /w

ls –o dir

pwd Check in which directory you are

cd cd

cd .. cd.. (Notice: You need a space

between cd and the dots in unix)

mv ren

rm del

mkdir md

rmdir rm

cp copy

/ \ (This is not a command, but observe

that the slash in unix has the other

orientation comparing to dos.)

One useful thing in Unix is when you are typing in a file-name you can write the beginning

## WDE.

and then press Then the operating system automatically appends the rest of the letters in

the file name (if there is no ambiguity in the file name). For example if you want to use a file

“my_circuit.blif” you can just type “my” and press tab.

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## )LOHIRUPDWVIRUFRPELQDWLRQDOORJLF

³%/,)´IRUPDWIRUFRPELQDWLRQDOORJLF

The BLIF (Berkeley Logic Interchange Format) is a format for describing combinational

circuits as a network of nodes. Each node is a single output function and is described as a

truth table. The truth table has entries for only those input combinations for which the output

is “1”. A bar “-“ can be used as a “don’t-care” on an input.

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A full-adder has three inputs, let us call them “i1”, “i2” and “cin” where “cin” means carry-in.

It has two outputs “sum” and “cout”. The truth table for this is:

i1 i2 cin sum cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

In BLIF-format this can be described as shown below. The orders in which the signals are

written on the line starting with “.names” are the order the ones and zeros in the table are

interpreted.

.inputs i1 i2 cin

.outputs sum cout

.names i1 i2 cin sum

001 1

010 1

100 1

111 1

.names i1 i2 cin cout

110 1

101 1

011 1

111 1

.end - 18 -

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We can also use the don’t-care-character “-“ and then it can be written as follows, which are

equivalent with the code on the previous page.

. i n p u t s i 1 i 2 c i n

. i n p u t s i 1 i 2 c i n

. o u t p u t s s u m c o u t

. o u t p u t s s u m c o u t

. n a m e s i 1 i 2 c i n s u m

. n a m e s i 1 i 2 c i n s u m

0 0 1 1

0 0 1 1

0 1 0 1

0 1 0 1

1 0 0 1

1 0 0 1

1 1 1 1

1 1 1 1

.names i1 i2 cin cout

11- 1

1-1 1

-11 1

. e n d

. e n d

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Comments can be put in to a file in “BLIF”-format. A comment starts with “#” and last to the

end of line.

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The command “write_blif” writes the description of the circuit in “BLIF”-format. There is

one more line, “.model”, which only tells the name of the circuit and it will automatically be

the file-name if nothing else is specified.

sis> write_blif

.model fa.blif

.inputs i1 i2 cin

.outputs sum cout

.names i1 i2 cin sum

111 1

001 1

010 1

100 1

.names i1 i2 cin cout

111 1

011 1

101 1

110 1

.end - 19 -

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When having larger systems it’s sometimes makes easy to be able to describe systems in a

hierarchical manner. To illustrate this a four-bit adder is used which is design with four full-

adders. The code below shows how it can be described in “BLIF”-format.

.inputs a3 a2 a1 a0 b3 b2 b1 b0

.outputs s3 s2 s1 s0 cout

.subckt fa a=a0 b=b0 cin=zero sum=s0 cout=cout0

.subckt fa a=a1 b=b1 cin=cout0 sum=s1 cout=cout1

.subckt fa a=a2 b=b2 cin=cout1 sum=s2 cout=cout2

.subckt fa a=a3 b=b3 cin=cout2 sum=s3 cout=cout

.names zero

.end

.model fa

.inputs a b cin

.outputs sum cout

.names a b cin sum

001 1

010 1

100 1

111 1

.names a b cin cout

11- 1

1-1 1

-11 1

.end

A description of a sub-cell starts with “.model” followed by a name on the sub-cell. It ends

with “.end”.

Before the first “.end” the top-level logic is described. A sub-cell is added as an instance by

first writing the key word “.subckt”. After that the name of the instance should be written.

Then a description follows that tells which signal in the top-block should be connected to

which in the sub-cell. The signal-name to the left of the “=”-sign is the name in the sub-cell

and the signal-name to the right is the name in the top-block.

Multi-level hierarchy is possible to use in “BLIF”-format.

The table below shows how to force a signal to “one” or “zero”.

.names s Assign constant value ”0” to the signal ”s”.

.names s Assign constant value ”1” to the signal ”s”.

1 - 20 -

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)LOHIRUPDW³3/$´ The “PLA”-format is quite similar to the “BLIF”-format. The example below is a description of the full-adder described in section “4.1.1 Example Full-adder”. .i 3 .i 3 .o 2 .o 2 .ilb i1 i2 cin .ilb i1 i2 cin .ob sum cout .ob sum cout 100 10 100 10 010 10 010 10 001 10 001 10 -11 01 111 10 1-1 01 011 01 11- 01 101 01 111 11 110 01 111 01 .e .e The first two rows “.i” and “.o” describes how many inputs and outputs the circuit has. The two following rows, “.ilb” and “.ob”, defines the names of the inputs and outputs. The definition of names is not needed. The “ones” and “zeros” in the table is the description of the logical function. The digits to the left are the inputs and the digits to the right are the outputs. A row in the table means that for the specified input-combination the outputs marked with “1” in the output-column should be “one”. The “zeros” in the output-column have another meaning. A “zero” there for an output, in a row, means that this row does not affect the function of that output. This can be a little misleading if you don’t know it. All combinations where an output has not been declared to be “one”, the output becomes “zero”. It’s also possible to use “-“ in the inputs to represent “don’t-cares”. If a combination of input should set more than one output to “one”, it can be described in one row. The example to the right in the squares above shows the same function, full-adder, as to the left, but described using don’t cares. - 21 - /RJLFRSWLPLVDWLRQXVLQJ6,6 7RPDV%HQJWVVRQ 7RPDV%HQJWVVRQ#LQJKMVH 6KDVKL.XPDU 6KDVKL.XPDU#LQJKMVH 7KHFRPPDQG³ZULWHBSOD´ The command “write_pla” writes the description of the circuit in “PLA”-format. There is one more line, “.p”, which only tells how many product-terms are there in the representation. sis> write_pla .i 3 .o 2 .ilb i1 i2 cin .ob sum cout .p 8 111 10 001 10 010 10 100 10 111 01 011 01 101 01 110 01 .e SODIRUPDWIRUIXQFWLRQVZLWKGRQ¶WFDUHV A function that has “don’t cares” is a function that for some combination of inputs, the output doesn’t cares. It is possible to use pla-format to describe this type of functions. If you want to specify that a combination of input is a “don’t care” you do as when you specify that it is one but instead of writing “1” in the output part you write “-“ or “2”. The example below shows a function and its corresponding pla-file. .i 2 .o 1 .ilb x1 x2 .ob out 01 1 10 1 11 – .e - 22 - /RJLFRSWLPLVDWLRQXVLQJ6,6 7RPDV%HQJWVVRQ 7RPDV%HQJWVVRQ#LQJKMVH 6KDVKL.XPDU 6KDVKL.XPDU#LQJKMVH 7KH³(41´IRUPDW The “EQN”-format stands for equation-format. This is a way to describe a logical network using Boolean equations. The example below shows how the full-adder can be described in the “EQN”-format. sum = i1*!i2*!cin + !i1*i2*!cin + !i1*!i2*cin + i1*i2*cin; cout = i1*i2*!cin + i1*!i2*cin + !i1*i2*cin + i1*i2*cin; Observe that every equation should be ended by “;”. The operators are: ! Inverse * And + Or It’s also possible to write equation with intermediate nodes. SIS computes in that case which nodes are outputs and inputs to the system. sum = i1*!i2*!cin + !i1*i2*!cin + !i1*!i2*cin + node*cin; cout = node*!cin + i1*!i2*cin + !i1*i2*cin + node*cin; node = i1*i2; 7KHFRPPDQG´ZULWHBHTQ´ This command writes the system on equation-form. There are two lines in the beginning describing which nodes are inputs and which are outputs. sis> write_eqn INORDER = i1 i2 cin; OUTORDER = sum cout; node = i1*i2; sum = i1*!i2*!cin + !i1*i2*!cin + !i1*!i2*cin + cin*node; cout = i1*!i2*cin + !i1*i2*cin + !cin*node + cin*node; - 23 - /RJLFRSWLPLVDWLRQXVLQJ6,6 7RPDV%HQJWVVRQ 7RPDV%HQJWVVRQ#LQJKMVH 6KDVKL.XPDU 6KDVKL.XPDU#LQJKMVH ## )LOHIRUPDWIRUVHTXHQWLDOORJLF ³.,66´IRUPDWDVXESDUWRI³%/,)´WRGHVFULEHDQ)60 The format “KISS2” is a sub format of “BLIF”. It is used to describe finite state-machines. Because it is a sub format to “BLIF” you can get some useful information with help of the command “write_blif”. It’s described in a way independent of the encoding of the states. The example below helps to describe the format. .start_kiss .i 2 .o 2 0-/00 .r s1 0- s1 s1 00 10 s1 s3 00 11 s1 s2 01 0- s2 s2 01 s1 10 s2 s1 01 11 s2 s3 10 0- s3 s3 10 11/01 10/00 1- s3 s1 11 .end_kiss .end 1-/11 10/01 s2 s3 11/10 0-/10 0-/01 .i 2 (number of inputs) .o 2 (number of outputs) .r s1 (defines start-state, useful during simulation) The rows after that describes: ## LQSXWVFXUUHQWBVWDWHQH[WBVWDWHRXWSXWV So the second line in this section, 10 s1 s3 00 V V . means that in state when the input is next state will be and the outputs - 24 - /RJLFRSWLPLVDWLRQXVLQJ6,6 7RPDV%HQJWVVRQ 7RPDV%HQJWVVRQ#LQJKMVH 6KDVKL.XPDU 6KDVKL.XPDU#LQJKMVH 6,6&RPPDQGV ,QSXW&RPPDQGV All commands starting with “read” (for example “read_kiss”) fall in this category. One of these commands must be run to convey the input specification to the circuit. A file name containing the input specification must be specified along with this type of commands. You can learn more about various formats to specify a circuit from a document downloadable from ## KWWSZZZEGGSRUWDORUJGRFXEOLIEOLIKWPO. ## UHDGBEOLI Read the circuit, which is described in BLIF format. For example, if the circuit in blif format ## FNWEOLI, is available in a file the command will be: read_blif ckt.blif There are similar commands to read the specification of the circuit in other formats. ## UHDGBDVWJ Read the specification given in Asynchronous State Transition Graph format. ## UHDGBHTQ Read the specification given in Equation format. ## UHDGBNLVV Read the specification given in KISS format. ## UHDGBSOD Read the specification given in PLA format. 3URFHVVLQJ&RPPDQGV These commands can be run only after input is conveyed to SIS through one of the input commands. If input is in state machine type, which is in KISS2 or ASTG format, first a circuit is to be generated and then optimization commands can be run. However, if input is already a circuit specification, only optimization commands need to run. (For circuit generation, commands like ‘state_minimize’ have to be used. For optimization, commands like ‘full_simplify’ are used). - 25 - /RJLFRSWLPLVDWLRQXVLQJ6,6 7RPDV%HQJWVVRQ 7RPDV%HQJWVVRQ#LQJKMVH 6KDVKL.XPDU 6KDVKL.XPDU#LQJKMVH 7ZR/HYHO2SWLPL]DWLRQ&RPPDQGV ## HVSUHVVR There is one “espresso” command that could be run from the UNIX prompt outside SIS. There is also one that works inside SIS. Unfortunately they behave differently. The one inside SIS divides multiple output functions into may single output functions and optimize them separately. The “espresso” command in the UNIX-prompt can however optimize a multiple output function so it takes advantage from common implicants between the outputs. In this lab you should use “espresso” at the UNIX prompt outside SIS. The espresso command is used for generating minimum cost circuit for “two level implementation”. The command minimizes the number of product terms needed in “two level optimization”. The output of “espresso” is an irredundant prime cover, often minimum in cardinality. For example, consider the following circuit in PLA format. It has six product terms. bash-2.04$ cat example.pla

.i 3

.o 2

.ilb a b c

.ob f1 f2

100 10

101 10

111 10

011 01

010 01

111 01

.e

bash-2.04$After using the Espresso command, the minimized circuit will be bash-2.04$ espresso example.pla

.i 3

.o 2

.ilb a b c

.ob f1 f2

.p 3

111 11

10- 10

01- 01

.e

bash-2.04$Notice the number of product terms after “two level” optimization has been reduced from six to three. - 26 - /RJLFRSWLPLVDWLRQXVLQJ6,6 7RPDV%HQJWVVRQ 7RPDV%HQJWVVRQ#LQJKMVH 6KDVKL.XPDU 6KDVKL.XPDU#LQJKMVH If you want the result in a file instead on the screen you can add a “>” symbol and then the name of the file. The box below shows an example. bash-2.04$ espresso example.pla > name_of_out_file

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## GHFRPS

This command decomposes an internal vertex into more than one internal node. Many times it

leads to reduction in number of literals. But this command, in general, leads to increase in

delay of the network.

Example : Consider a circuit in equation format:

sis>write_eqn

INORDER = b e c d a;

OUTORDER = v;

v = !e*a + !c*d + b*d + e*!c + b*e;

sis>

After decomposition using decomp command:

sis> decomp

sis> write_eqn

INORDER = b e c d a;

OUTORDER = v;

v = [2]*[1] + !e*a;

[1] = d + e;

[2] = !c + b;

sis> - 27 -

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## HOLPLQDWHN

It removes internal vertices from the network if its removal will not increase the number of

literals by more than k . The variable corresponding to the vertex is replaced by the

## GHFRPS.

corresponding expression in all its occurrences. This command is reverse of This

command helps in reducing the delay of the network.

Let the starting network in Equation format be:

sis> write_eqn

INORDER = b e c d a;

OUTORDER = v;

v = [4]*[3] + !e*a;

[3] = d + e;

[4] = !c + b;

sis> HOLPLQDWH

After applying command, the new network will be:

sis> write_eqn

INORDER = b e c d a;

OUTORDER = v;

v = d*[4] + e*[4] + !e*a;

[4] = !c + b;

sis>

Notice that node [3] has been eliminated. - 28 -

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## VLPSOLI\DQGIXOOBVLPSOLI\

These command are used to simplify the specification of each of the node in the network.

Initial network:

sis> write_eqn

INORDER = a b c;

OUTORDER = v w;

v = a*!b*c + !a*!c + a*b;

w = !a*!b + a;

sis> VLPSOLI\

After using command

sis> write_eqn

INORDER = a b c;

OUTORDER = v w;

v = b*w + !a*!c + a*c;

w = !b + a;

sis> IXOOBVLPSOLI\ VLPSOLI\.

Sometimes may lead to better results than

## LQYHUW

Implement the ‘inverse’ of the node. Many times it simplifies the specification of network.

Consider the following function:

sis> write_eqn

INORDER = a c d e g b;

OUTORDER = f;

F = g*b + e*b + d*b + c*b + a*g + a*e + a*d + a*c;

sis> LQYHUWI

By using command, we get:

sis> write_eqn

INORDER = a c d e g b;

OUTORDER = f;

[0] = !c*!d*!e*!g + !a*!b;

f = ![0];

sis>

## LQYHUWBLR

Use complemented input variables or produce a complemented output.

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## I[

This command extracts common sub-expressions among the nodes and rewrites the nodes of

the network in terms of common sub-expressions. The following example illustrates the use

## I[

of command.

sis> write_eqn

INORDER = a b c d e;

OUTORDER = w x y z;

w = a*!e + !c*d + b*d + !a*d;

x = d*e + c*e + !b + !a;

y = b*d + a*d + b*c + a*c + e;

z = c + b + a;

sis> fx

sis> write_eqn

INORDER = a b c d e;

OUTORDER = w x y z;

w = a*!e + !c*d + b*d + !a*d;

x = e*[4] + !b + !a;

y = [4]*[5] + e;

z = [5] + c;

[4] = d + c;

[5] = b + a;

sis>

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## UHVXE

The commandUHVXEtry to substitute expression corresponding to one node in expressions

corresponding to other nodes. The purpose is to reuse the expression of a node as sub

expression in some other nodes. This step is expected to reduce the number of literals in the

circuit.

For example, consider the following network in equation format.

sis> write_eqn

INORDER = a c d b;

OUTORDER = u v;

u = c*b + a*d + a*!c;

v = d + !c;

sis> UHVXE

After using command, the network will be

sis> write_eqn

INORDER = a c d b;

OUTORDER = u v;

u = a*v + c*b;

v = d + !c;

sis>

Notice that node “u” has been rewritten in terms of “v”.

## VZHHS

Sweep command eliminates all single input vertices and those with a constant value.

Consider the following network:

sis> write_eqn

INORDER = a c d b;

OUTORDER = u v;

u = a*v + c*b;

v = [2];

[2] = d + !c;

sis>

After applying sweep command, the new network will be

sis> write_eqn

INORDER = a c d b;

OUTORDER = u v;

u = a*v + c*b;

v = d + !c;

sis> - 31 -

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## UHGXFHBGHSWK

This command is used to control the delay of the network during multi-level logic

optimization. The following example illustrates the use of this command.

sis> write_blif

.model rd.blif

.inputs a b c d e

.outputs x

.names e r x

11 1

.names a b p

11 1

.names c p q

11 1

.names d q r

11 1

.end

sis> print_level

0: a e d c b

1: p

2: q

3: r

4: {x}

The network has depth of 4 levels. The depth can be reduced to 2-levels by using the

command “UHGXFHBGHSWK±GN”, where k gives the number of levels in the reduced network.

sis> reduce_depth -d 2

sis> print_level

0: b e a d c

1: q

2: {x}

sis> write_blif

.model rd.blif

.inputs a b c d e

.outputs x

.names d e q x

111 1

.names a b c q

111 1

.end - 32 -

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5XJJHGVFULSW

Rugged-script is not a command but a script containing a sequence of multilevel optimization

Logic Optimization”.

)60RSWLPL]DWLRQFRPPDQGV

## VWDWHBPLQLPL]H

Minimizes the number of states in a given FSM. Consider the following FSM that has one

input , 3 outputs and 6 states.

sis> write_kiss

.i 1

.o 3

.p 12

.s 6

.r s0

0 s0 s0 000

1 s0 s1 000

0 s1 s1 001

1 s1 s2 001

0 s2 s2 010

1 s2 s3 010

0 s3 s3 011

1 s3 s4 011

0 s4 s4 100

1 s4 s5 100

0 s5 s4 100

1 s5 s0 100

sis> - 33 -

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+1 anno fa

### DESCRIZIONE DISPENSA

SIS is a tool from University of Berkeley, California, which incorporate a set of Logic Optimization techniques. It has techniques for optimization and implementation of both Combinational Circuits (Boolean Functions) and Sequential Circuits (Finite-state machine). SIS uses special formats for representation of Boolean Functions, combinational circuits and Finite-state machines (FSMs).

DETTAGLI
Corso di laurea: Corso di laurea magistrale in ingegneria delle telecomunicazioni
SSD:
Università: L'Aquila - Univaq
A.A.: 2011-2012

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher Atreyu di informazioni apprese con la frequenza delle lezioni di Sistemi embedded e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università L'Aquila - Univaq o del prof Pomante Luigi.

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