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SIS is a tool from University of Berkeley, California, which incorporate a set of Logic Optimization techniques. It has techniques for optimization and implementation of both Combinational Circuits (Boolean Functions) and Sequential Circuits (Finite-state machine). SIS uses special formats for representation... Vedi di più

Esame di Sistemi embedded docente Prof. L. Pomante

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Before a system is implemented in hardware, it is required to get the structure of the system in

terms of hardware components. Logic Synthesis generates the circuit in terms of gates and

flip-flops. Generally, Logic Synthesis has cost minimization (in terms of number of gates or

transistors) as its main objective. But sometimes, it is required to implement the circuit so that

it has minimum delay or fastest clock. Before generating the final implementation, optimizing

transformations are applied to the system representation so as to get an equivalent

representation that leads to implementation meeting the desired objectives. If the size of the

system is large then these techniques cannot be manually applied and computer tools are

required to do this job.

SIS is a tool from University of Berkeley, California, which incorporates a set of Logic

Optimization techniques. It has techniques for optimization and implementation of

bothCombinational Circuits (Boolean Functions) and Sequential Circuits (Finite State

Machines). SIS uses special formats for representation of Boolean functions, combinational

circuits and Finite State Machines (FSMs).

You will learn about the theory of techniques for Logic Synthesis in the lecture classes. The

purpose of laboratory exercises is to get hands-on experience in using the SIS tool for Logic

Synthesis.

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To get experience with SIS tool, or CAD tools in general, we need to use a large number of

example circuits. Generating these circuits is a time consuming activity. Many CAD tool

designers and researchers have collected many such examples and designs and they have

made them available on the Internet for other people to use. Such design examples are

available at various levels of design and for various purposes. Such collections of design

examples are called benchmark circuits. A large variety of combinational and sequential

benchmark circuits are available for learning and experimenting with logic synthesis tools.

The benchmark circuits include adders and multipliers of various types; encoders and

decoders; controllers for various applications etc.

Benchmarks circuits are also used for comparing and evaluating the performance of various

CAD tools or CAD algorithms. - 4 -

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The objectives of the first laboratory are:

1. Learn formats for representation of combinational and sequential circuits.

a. Combinational Circuit: BLIF, PLA, EQUATION formats

b. Sequential Circuits: KISS

2. Learn SIS commands for combinational and sequential circuit optimization

3. Design and optimize a combinational circuit for a BCD to 7-segment display decoder

using SIS

a. Describe the circuit in PLA format

b. Optimize the circuit for two-level (PLA) implementation

4. Design and optimize a combinational circuit for 4 bit multiplier using SIS

a. Describe the circuit in BLIF format

c. Optimize the circuit for multi-level optimization

5. Design and optimize a sequential circuit

a. Describe the FSM using KISS format

b. Optimize using SIS commands

6. Practice the use of SIS tool to optimize three combinational benchmark circuits and

three sequential benchmark circuits.

7. Estimate the advantage obtained by the use of SIS optimization tool in different types

of designs.

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A form is provided fro this laboratory in which you should fill in your results. One sheet of

paper written by Arne Ståhl about how to open the UNIX account will also be provided, see

section “3.1 How to start up your UNIX account” in this manual.

There is also a home page, which contains the lab manuals and some related documents. Its

address is “http://hem.hj.se/~beto/courses/logic_optimization/main.html”. There you can find

among other things, a link to a document about SIS and one document about BLIF format. In

Pingpong you can find those documents converted to pdf-format.

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In this task you should design a BCD to 7-segment display decoder. Before you come to the

lab you should have described two versions of it in PLA-format, see part “2.1.3 Information

about BCD to 7-segment decoder” in this manual. Don’t try to optimize it by hand when you

are writing the PLA-format, just write it in the way that feels most simple for you. Then in the

lab, the tool will help you to optimize.

You should also design a 4-bit unsigned multiplier and describe it in “BLIF”-format. It should

be a pure combinational multiplier without memory-elements. Before you come to the lab you

should have thought out how this multiplier should be built and also written this in “BLIF”-

format. A 4-bit multiplier has two 4-bit numbers as input. As output it has as many bits as

needed to be able to represent every possible product.

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Use “SIS” to optimize your two versions of the BCD to 7-segment decoder. Make two level

optimization and fill in the required data in the hand in form.

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A BCD to 7-segment decoder is a combinational circuit with four inputs and seven outputs.

Its purpose is to convert a BCD number to information to every segment telling if it should be

on or off. In some decoders if the inputs are between and the decoder outputs

1010 1111

values making the display showing the corresponding hexadecimal letters. When this is not

needed it is however better to let the outputs be don’t cares, to make the logic smaller. In this

lab you should make the outputs don’t cares for inputs and higher. Then you should

1010

make two version of the decoder, one where the don’t cares is forced to zero and one where

they are treated as don’t cares.

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First you should validate that your multiplier works, in other words check that the function is

correct. Use the “SIS”-command “simulate” which is described in part “6.6 Miscellaneous

Commands” in this document. (You don’t have to simulate your BCD to 7-segment decoder

in this way.)

Use “SIS” to optimize your 4-bit multiplier. Use a sequence of multi level optimization

operations so you get less than 167 literals. Read in your multiplier again and optimize it with

rugged script. Compare the result from your optimization with the result rugged script gives.

Write in the “hand-in” form what is required.

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Next task is to convert the multiplier so it gets only two levels of logic. Use the command

“UHGXFHBGHSWK” to achieve this. Fill in the “hand-in” form how many literals you get.

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Here is an example of multiplying two binary numbers, which shows the principal of

multiplying. Assume that 1011 and 1101 should be multiplied. A simplifying observation is

that when two binary digits, which only can have value “zero” and “one”, are multiplied, it is

similar to the and-function. Write the calculation like this.

1 0 1 1

* 1 1 0 1 Take the least significant digit, the most right, in the number

1 0 1 1 written on the lower line and multiply it with the upper number.

* 1 1 0 1

1 0 1 1 Continue and multiply the number on the upper line with every

1 0 1 1 digit on the lower line and write the products below and

* 1 1 0 1 adjusted to the left which means multiplied with 10, 100 and so

1 0 1 1 on.

0 0 0 0

1 0 1 1

1 0 1 1 Add those numbers that you’ve got now with respect to their

1 0 1 1 position.

* 1 1 0 1

1 0 1 1

0 0 0 0

1 0 1 1

+ 1 0 1 1

1 0 0 0 1 1 1 1

When designing the multiplier, don’t forget to think about where carries can come out from

adders and how they should be connected to get the multiplier work.

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In this task you should design a four bit sequential circuit for Gray-code to binary code

conversion. The Gray code is sent into the code converter bet serially as well as the binary

output is sent bit serially from the code converter. In both input and output the bits are starting

with most significant bit and ending with the least significant bit. There is no pause between

data words coming into the code converter. In other words one clock cycle after the least

significant bit is put into the code converter, the most significant bit of the subsequent word is

enters the converter.

If this converter should work in reality it is important to force it to a specific state when it

starts up. Anyway in this lab we don’t bother about how to get there but just assuming that we

can get there in some way.

The properties of the Gray code is in a way such that the conversion described above can be

done without any delay from input to output in terms of clock cycles. That is only when bits

comes starting with most significant bit and ending with least significant bit.

Before the lab, you should design a FSM that makes a converter as described above. It should

not have any delay from input to output in terms of clock cycles. Observe that you should not

try to make the number of states in the state machine small. This work you should let the SIS-

tool do when you are at the lab. You should also have made a description of this FSM in

“KISS2”-format.

In the “hand-in” form you should show how the state diagram look like before optimization.

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Use “SIS” to minimize number of states in the FSM. Then let “SIS” assign the coding of the

states. Try both to assign for minimal number of flip-flops and for one-hot encoding. Try to

minimize the logic in the FSM in both cases. Write down required data in the “hand-in” form.

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Gray Binary

code code

0000

0000 0001

0001 0010

0011 0011

0010 0100

0110 0101

0111 0110

0101 0111

0100 1000

1100 1001

1101 1010

1111 1011

1110 1100

1010 1101

1011 1110

1001 1111

1000

The table above shows a conversion table between four bit Gray code and four bit binary

code. The Gray code is used in some devices where it is required that only one bit differs

between adjacent code words.

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Read about benchmarks in part

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In this task you should optimize some benchmarks with “SIS”. In directory

³KRPHEHWRSXEOLFORJLFBV\QWKHVLVEHQFKPDUNV´ the benchmarks are stored. Make

appropriate directories in your home directory and copy the benchmarks to them.

The benchmarks are also possible to download from Internet at address:

http://www-cad.eecs.berkeley.edu/Software/software.html

Some of the benchmarks may not work so in this case just try another one.

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You should select three of the benchmarks of combinational circuits described in pla-format

and do two-level optimization of them. Fill in the number of product terms before and after

minimization in the hand in form.

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You should select three of the benchmarks of combinational circuits described in blif-format.

Try to use the same sequence of commands you used for optimizing the multiplier. Optimize

them also with help of rugged-script. Fill in the required information in the hand in form.

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Select three of the sequential benchmarks. Use “SIS” to minimize number of states. Then let

“SIS” assign the coding of the states. Try both to assign for minimal number of flip-flops and

for one-hot encoding. Try to minimize the logic in the FSM in both cases. Write down

required data in the hand in form.

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The software “SIS” has to be run under Unix. It is a text-based software so using “Telnet”

will be suitable but if you can use “ReflextionX” it will probably look better.

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To get you UNIX work you first have to telnet to “junic”. For instructions about this see the

one page document “SYNKRONISERA LÖSENORD (NISCLIENT)” made by Arne Ståhl.

The username is the same as in Novell netware and the password is the password you got

from the beginning when you get your computer account to the Novell netware. If you have

forgotten you can ask the lab assistant.

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In the text below it is assumed that you make remote-login to the computer “gustav.hj.se”.

You should replace this in the description below with “ ” because the

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computer “gustav.hj.se” is not so good. - 10 -

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To start “Telnet” choose “Run” from “Windows” start-menu. Key in “telnet” and press

UHWXUQ. Select “Connect” -> “Remote system…”. Then fill in the up-popping window as the

picture below shows, click on “Connect” and follow the instructions.

You will hopefully now get into a Unix-environment.

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The picture below shows how to start “ReflextionX”. It maybe looks different on some

computers. Sometimes this program may hang the PC.

If you are using a computer with Windows98 the resolution of the screen maybe adjusted

lower than 1024*768 pixels. If this is the case, you get a better-looking UNIX environment if

you change to 1024*768 pixels before you start ReflextionX. If you don’t know how to do

this in Windows98 you can ask the lab assistent.

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When this program is started it looks as below

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Click on some of the lines starting with the left. Fill in the settings in the square

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in the right lower corner. Then click on Maybe you have to

experiment and try some other settings in ReflextionX to get in.

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You will come to a login screen. Before you log in you can chose between two different

window-system from a menu, “Open Windows” and “Common Desktop Environment

(CDE)”. We recommend you to use “Common Desktop Environment (CDE)” because we

have found it difficult to handle “Open Windows” when logging in via “ReflectionX”.

Normally if you are logging in you get into the window-system you used last time. The

picture below shows how to select “Common Desktop Environment (CDE)”.

When you have logged in to the Unix, right-click somewhere and you will get a menu. To get

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a terminal-window choose and then

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When you are coming in to the Unix-system, you will probably come into “C-shell” which

does not have some good features in our system. This is the case if the prompt is a “$”-sign.

To get a more user-friendly system you can run a program that adjusts the environment. This

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you should run only once. Do this by typing:

cd /usr/sw/

./install_modules.sh - 14 -

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When you have done this you can get into a better shell by typing but before that it is

good to make file, which makes the path to “SIS” and some other good things, when you start

EDVK. You can do that by coping a file which already exists. Do it by typing the following

command:

cd

cp /home/beto/public/.bashrc .

You can now give the command:

bash HPDFVby

If everything has worked you can now run the editor typing:

emacs

If you have logged in via “ReflextionX” you can put the symbol “&” after if you want to start

HPDFV as an independent window, otherwise you are not able to use the terminal you started

HPDFV HPDFV.

from until you exit

If you want whit background instead of white you can type:

emacs –bg white - 15 -

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If you want to transport files between windows and UNIX, for example descriptions of

circuits you have done, you can use an ftp-software. Start this software from Windows start

menu by choosing:

Start -> Internetapplikationer -> Ws_ftp -> WS_FTP95 LE

Observe that there are two “Internetapplikationer” and you should choose the lower one to

find this. You should then fill in the box as shown in the figure below but change the stars to

your Unix-account user-id and password.

When you’ve done this and click on “OK” you’ll get a window, which shows your windows-

files to the left and unix-files to the right. If you want to copy a file from one system to

another you just mark it and click on the arrow-button in the middle pointing in the direction

in which the copying should be done. - 16 -

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To start “SIS” you should type in the Unix-prompt and then you’ll get in if the

“sis”

settings described in part 3.5 has worked out. To exit “SIS”, write the command quit.

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The “SIS” user-interface is a command-based software. This means that you have a command

prompt in which you have to write commands to make things happen.

The normal backspace and arrow key does not work in SIS. The two following key

combinations could be used for correcting mistakes.

Ctrl – h backspace

Ctrl – w delete last word

There is not much help included in the SIS software but you can at least get a list of available

KHOS.

commands by giving command

If you read in a file that have some errors in the format SIS may get into a state that makes it

behave strange. In this case quit SIS and start it again. There could be other similar strange

behavior by other mistake commands.

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Here follows a list with some Unix-commands. Observe that Unix is sensitive to if you use

capital letters or small letters.

UNIX-command Explanation or corresponding DOS-

command

ls dir /w

ls –o dir

pwd Check in which directory you are

cd cd

cd .. cd.. (Notice: You need a space

between cd and the dots in unix)

mv ren

rm del

mkdir md

rmdir rm

cp copy

/ \ (This is not a command, but observe

that the slash in unix has the other

orientation comparing to dos.)

One useful thing in Unix is when you are typing in a file-name you can write the beginning

WDE.

and then press Then the operating system automatically appends the rest of the letters in

the file name (if there is no ambiguity in the file name). For example if you want to use a file

“my_circuit.blif” you can just type “my” and press tab.

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The BLIF (Berkeley Logic Interchange Format) is a format for describing combinational

circuits as a network of nodes. Each node is a single output function and is described as a

truth table. The truth table has entries for only those input combinations for which the output

is “1”. A bar “-“ can be used as a “don’t-care” on an input.

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A full-adder has three inputs, let us call them “i1”, “i2” and “cin” where “cin” means carry-in.

It has two outputs “sum” and “cout”. The truth table for this is:

i1 i2 cin sum cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

In BLIF-format this can be described as shown below. The orders in which the signals are

written on the line starting with “.names” are the order the ones and zeros in the table are

interpreted.

.inputs i1 i2 cin

.outputs sum cout

.names i1 i2 cin sum

001 1

010 1

100 1

111 1

.names i1 i2 cin cout

110 1

101 1

011 1

111 1

.end - 18 -

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We can also use the don’t-care-character “-“ and then it can be written as follows, which are

equivalent with the code on the previous page.

. i n p u t s i 1 i 2 c i n

. i n p u t s i 1 i 2 c i n

. o u t p u t s s u m c o u t

. o u t p u t s s u m c o u t

. n a m e s i 1 i 2 c i n s u m

. n a m e s i 1 i 2 c i n s u m

0 0 1 1

0 0 1 1

0 1 0 1

0 1 0 1

1 0 0 1

1 0 0 1

1 1 1 1

1 1 1 1

.names i1 i2 cin cout

11- 1

1-1 1

-11 1

. e n d

. e n d

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Comments can be put in to a file in “BLIF”-format. A comment starts with “#” and last to the

end of line.

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The command “write_blif” writes the description of the circuit in “BLIF”-format. There is

one more line, “.model”, which only tells the name of the circuit and it will automatically be

the file-name if nothing else is specified.

sis> write_blif

.model fa.blif

.inputs i1 i2 cin

.outputs sum cout

.names i1 i2 cin sum

111 1

001 1

010 1

100 1

.names i1 i2 cin cout

111 1

011 1

101 1

110 1

.end - 19 -

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When having larger systems it’s sometimes makes easy to be able to describe systems in a

hierarchical manner. To illustrate this a four-bit adder is used which is design with four full-

adders. The code below shows how it can be described in “BLIF”-format.

.inputs a3 a2 a1 a0 b3 b2 b1 b0

.outputs s3 s2 s1 s0 cout

.subckt fa a=a0 b=b0 cin=zero sum=s0 cout=cout0

.subckt fa a=a1 b=b1 cin=cout0 sum=s1 cout=cout1

.subckt fa a=a2 b=b2 cin=cout1 sum=s2 cout=cout2

.subckt fa a=a3 b=b3 cin=cout2 sum=s3 cout=cout

.names zero

.end

.model fa

.inputs a b cin

.outputs sum cout

.names a b cin sum

001 1

010 1

100 1

111 1

.names a b cin cout

11- 1

1-1 1

-11 1

.end

A description of a sub-cell starts with “.model” followed by a name on the sub-cell. It ends

with “.end”.

Before the first “.end” the top-level logic is described. A sub-cell is added as an instance by

first writing the key word “.subckt”. After that the name of the instance should be written.

Then a description follows that tells which signal in the top-block should be connected to

which in the sub-cell. The signal-name to the left of the “=”-sign is the name in the sub-cell

and the signal-name to the right is the name in the top-block.

Multi-level hierarchy is possible to use in “BLIF”-format.

The table below shows how to force a signal to “one” or “zero”.

.names s Assign constant value ”0” to the signal ”s”.

.names s Assign constant value ”1” to the signal ”s”.

1 - 20 -

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The “PLA”-format is quite similar to the “BLIF”-format. The example below is a description

of the full-adder described in section “4.1.1 Example Full-adder”.

.i 3

.i 3 .o 2

.o 2 .ilb i1 i2 cin

.ilb i1 i2 cin .ob sum cout

.ob sum cout 100 10

100 10 010 10

010 10 001 10

001 10 -11 01

111 10 1-1 01

011 01 11- 01

101 01 111 11

110 01

111 01 .e

.e

The first two rows “.i” and “.o” describes how many inputs and outputs the circuit has. The

two following rows, “.ilb” and “.ob”, defines the names of the inputs and outputs. The

definition of names is not needed.

The “ones” and “zeros” in the table is the description of the logical function. The digits to the

left are the inputs and the digits to the right are the outputs. A row in the table means that for

the specified input-combination the outputs marked with “1” in the output-column should be

“one”. The “zeros” in the output-column have another meaning. A “zero” there for an output,

in a row, means that this row does not affect the function of that output. This can be a little

misleading if you don’t know it. All combinations where an output has not been declared to

be “one”, the output becomes “zero”.

It’s also possible to use “-“ in the inputs to represent “don’t-cares”. If a combination of input

should set more than one output to “one”, it can be described in one row. The example to the

right in the squares above shows the same function, full-adder, as to the left, but described

using don’t cares. - 21 -


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Atreyu

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+1 anno fa


DESCRIZIONE DISPENSA

SIS is a tool from University of Berkeley, California, which incorporate a set of Logic Optimization techniques. It has techniques for optimization and implementation of both Combinational Circuits (Boolean Functions) and Sequential Circuits (Finite-state machine). SIS uses special formats for representation of Boolean Functions, combinational circuits and Finite-state machines (FSMs).


DETTAGLI
Corso di laurea: Corso di laurea magistrale in ingegneria delle telecomunicazioni
SSD:
Università: L'Aquila - Univaq
A.A.: 2011-2012

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher Atreyu di informazioni apprese con la frequenza delle lezioni di Sistemi embedded e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università L'Aquila - Univaq o del prof Pomante Luigi.

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