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ESTRATTO DOCUMENTO

Metodologie di progetto HW

Il test di circuiti digitali

Introduction

VLSI Realization Process

Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification

Test development

Fabrication

Manufacturing test

Chips to customer

- 3 -

Present and Future*

1997 -2001 2003 - 2006

Feature size (micron) 0.25 - 0.15 0.13 - 0.10

Transistors/sq. cm 4 - 10M 18 - 39M

Pin count 100 - 900 160 - 1475

Clock rate (MHz) 200 - 730 530 - 1100

Power (Watts) 1.2 - 61 2 - 96

IEEE Spectrum

* SIA Roadmap, , July 1999

- 4 -

Testing Principle - 5 -

Contract between design house and

fab vendor

Design is complete and checked (verified)

‰ Fab vendor: How will you test it?

‰ Design house: I have checked it and …

‰ Fab vendor: But, how would you test it?

‰ Desing house: Why is that important?

‰ complete the story

That is one reason for test generation etc.

‰ - 6 -

Contract between design …

Hence:

“Test” must be comprehensive

‰ It must not be “too long”

‰

Issues:

Model possible defects in the process

‰ Understand the process

Develop simulator and fault simulator

‰ Develop test generator

‰ Methods to quantify the test efficiency

‰ - 7 -

Verification v/s Testing

Definitions

Design synthesis: Given an I/O function, develop a

‰ procedure to manufacture a device using known

materials and processes.

Verification: Predictive analysis to ensure that the

‰ synthesized design, when manufactured, will perform the

given I/O function.

Test: A manufacturing step that ensures that the physical

‰ device, manufactured from the synthesized design, has

no manufacturing defect. - 8 -

Need for testing

Functionality issue

‰ Does the circuit (large or small) work?

Density issue

‰ ⇒

Higher density higher failure prob

Application issue

‰ Life critical applications

Maintenance issue

‰ Need to identify failed components

Cost of doing business

‰ What does testing achieve?

‰ Discard only the “bad product”? – see next three slides

– - 9 -

Problems of Ideal Tests

Ideal tests detect all defects produced in the

‰ manufacturing process.

Ideal tests pass all functionally good devices.

‰ Very large numbers and varieties of possible

‰ defects need to be tested.

Difficult to generate tests for some real defects.

‰ Defect-oriented testing is an open problem.

- 10 -

Real Tests

Based on analyzable fault models, which may not

‰ map on real defects.

Incomplete coverage of modeled faults due to

‰ high complexity.

Some good chips are rejected. The fraction (or

‰ percentage) of such chips is called the yield loss.

Some bad chips pass tests. The fraction (or

‰ percentage) of bad chips among all passing chips

is called the defect level.

- 11 -

Testing as Filter Process Mostly

Good chips Prob(pass test) = high good

Pr

Prob(good) = y w

ob chips

o

l

(fa =

st)

il e

t

t es

Fabricated t)

s

chips s =

a lo

p

( w

b

o

Pr Mostly

Defective chips bad

Prob(bad) = 1- y Prob(fail test) = high chips

- 12 -

Level of testing (1)

Levels

‰ Chip

– Board

– System

– Boards put together

• System-on-Chip (SoC)

System in field

Cost – Rule of 10

‰ It costs 10 times more to test a device as we move to

– higher level in the product manufacturing process

- 13 -

Cost of Manufacturing

Testing in 2000AD

0.5-1.0GHz, analog instruments,1024 digital pins: ATE

‰ purchase price

= $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation)

‰ = Depreciation + Maintenance + Operation

– = $0.854M + $0.085M + $0.5M

– = $1.439M/year

Test cost (24 hour ATE operation)

‰ = $1.439M/(365 x 24 x 3,600)

– = 4.5 cents/second

– - 14 -

Metodologie di progetto HW

Il test di circuiti digitali

Fault Modeling

Why Model Faults?

I/O function tests inadequate for manufacturing

‰ (functionality versus component and interconnect testing)

Real defects (often mechanical) too numerous and often

‰ not analyzable

A fault model identifies targets for testing

‰ A fault model makes analysis possible

‰ Effectiveness measurable by experiments

‰ - 16 -

Some Real Defects in Chips

Processing defects

ƒ Missing contact windows

ƒ Parasitic transistors

ƒ Oxide breakdown

ƒ . . .

ƒ

Material defects

ƒ Bulk defects (cracks, crystal imperfections)

ƒ Surface impurities (ion migration)

ƒ . . .

ƒ

Time-dependent failures

ƒ Dielectric breakdown

ƒ Electromigration

ƒ . . .

ƒ

Packaging failures

ƒ Contact degradation

ƒ Seal leaks

ƒ . . .

ƒ Reliability and Degradation -

Ref.: M. J. Howes and D. V. Morgan,

Semiconductor Devices and Circuits, Wiley, 1981.

- 17 -

Observed PCB Defects

Occurrence frequency (%)

Defect classes 51

Shorts 1

Opens 6

Missing components 13

Wrong components 6

Reversed components 8

Bent leads 5

Analog specifications 5

Digital logic 5

Performance (timing)

In-Circuit Testing

Ref.: J. Bateson, , Van Nostrand Reinhold, 1985.

- 18 -

Common Fault Models

Single stuck-at faults

‰ Transistor open and short faults

‰ Memory faults

‰ PLA faults (stuck-at, cross-point, bridging)

‰ Functional faults (processors)

‰ Delay faults (transition, path)

‰ Analog faults

‰ - 19 -

Stuck -

at Faults

Single stuck-at faults

‰ What does it achieve in practice?

‰ Fault equivalence

‰ Fault dominance and checkpoint theorem

‰ Classes of stuck-at faults and multiple faults

‰ - 20 -

Single Stuck -

at Fault

Three properties define a single stuck-at fault

‰ Only one line is faulty

• The faulty line is permanently set to 0 or 1

• The fault can be at an input or output of a gate

Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at

‰ faults Faulty circuit value

Good circuit value

j

c 0(1)

s-a-0

d

a 1(0)

g h

1 z

i

0 1

e

b 1

k

f h

Test vector for s-a-0 fault

- 21 -

Single Stuck -

at Faults (contd.)

How effective is this model?

‰ Empirical evidence supports the use of this model

– Has been found to be effective to detect other types

– of fauls

Relates to yield modeling

– Simple to use

– - 22 -

Origins of Stuck -

Faults

Eldred (1959) – First use of structural testing for the

‰ Honeywell Datamatic 1000 computer

Galey, Norby, Roth (1961) – First publication of stuck-at-

‰ 0 and stuck-at-1 faults

Seshu & Freeman (1962) – Use of stuck-faults for parallel

‰ fault simulation

Poage (1963) – Theoretical analysis of stuck-at faults

‰ - 23 -

Fault Equivalence

Number of fault sites in a Boolean gate circuit = #PI + #gates + #

‰ (fanout branches).

Fault equivalence: Two faults f1 and f2 are equivalent if all tests that

‰ detect f1 also detect f2.

If faults f1 and f2 are equivalent then the corresponding faulty

‰ functions are identical.

Fault collapsing: All single faults of a logic circuit can be divided into

‰ disjoint equivalence subsets, where all faults in a subset are mutually

equivalent. A collapsed fault set contains one fault from each

equivalence subset. - 24 -

Equivalence Rules sa0 sa0

sa1

sa1

sa0 sa1 sa0 sa1 WIRE

sa0 sa1 sa0 sa1

AND OR

sa0 sa1 sa0 sa1 sa0 sa1

NOT sa0

sa1

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1 sa0

NAND NOR sa1

sa0

sa0 sa1 sa0 sa1 sa1 sa0

sa1

FANOUT

- 25 -

Equivalence Example

sa0 sa1 Faults in red

sa0 sa1 removed by

sa0 sa1 equivalence

collapsing

sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1 20

Collapse ratio = ----- = 0.625

32

- 26 -


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DESCRIZIONE DISPENSA

Design synthesis, given an I/O function, develop a procedure to manufacture a device using known materials and processes.
Verification is a predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.
Test is a manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.


DETTAGLI
Corso di laurea: Corso di laurea magistrale in ingegneria delle telecomunicazioni
SSD:
Università: L'Aquila - Univaq
A.A.: 2011-2012

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher Atreyu di informazioni apprese con la frequenza delle lezioni di Sistemi embedded e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università L'Aquila - Univaq o del prof Pomante Luigi.

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