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Embedded Systems Technology - General-Purpose Processors: Software Appunti scolastici Premium

General-Purpose Processor are:
– Processor designed for a variety of computation tasks;
– Low unit cost, in part because manufacturer spreads NRE over large numbers of units (Motorola sold half a billion 68HC05 microcontrollers in 1996 alone);
– Carefully designed since higher NRE is acceptable (can yield good performance, size and power);
–... Vedi di più

Esame di Sistemi embedded docente Prof. L. Pomante

Anteprima

ESTRATTO DOCUMENTO

Instruction Cycles

PC= Processor

100 Fetch Store Control unit Datapath

Fetch Decode Exec.

ops results ALU

clk Controller Control

/Status Registers

10

PC IR

100 R0 R1

load R0, M[500] I/O ...

Memory

100 load R0, M[500] 10

500

101 inc R1, R0 501 ...

102 store M[501], R1

Embedded Systems Design: A Unified 11

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Instruction Cycles

PC= Processor

100 Fetch Store Control unit Datapath

Fetch Decode Exec.

ops results ALU

+1

clk Controller Control

/Status

PC=

101 Registers

Fetch Store

Fetch Decode Exec.

ops results

clk 10 11

PC IR

101 R0 R1

inc R1, R0 I/O ...

Memory

100 load R0, M[500] 10

500

101 inc R1, R0 501 ...

102 store M[501], R1

Embedded Systems Design: A Unified 12

Hardware/Software Introduction, (c) 2000 Vahid/Givargis 6

Instruction Cycles

PC= Processor

100 Fetch Store Control unit Datapath

Fetch Decode Exec.

ops results ALU

clk Controller Control

/Status

PC=

101 Registers

Fetch Store

Fetch Decode Exec.

ops results

clk 10 11

PC IR

102 R0 R1

store M[501], R1

PC=

102 Fetch Store

Fetch Decode Exec. I/O

ops results ...

Memory

100 load R0, M[500] 10

500

clk 101 inc R1, R0 11

501 ...

102 store M[501], R1

Embedded Systems Design: A Unified 13

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Architectural Considerations

• N-bit processor Processor

Control unit Datapath

– N-bit ALU, registers, ALU

buses, memory data Controller Control

interface /Status

– Embedded: 8-bit, 16- Registers

bit, 32-bit common

– Desktop/servers: 32- PC IR

bit, even 64

• PC size determines I/O

address space Memory

Embedded Systems Design: A Unified 14

Hardware/Software Introduction, (c) 2000 Vahid/Givargis 7

Architectural Considerations

• Clock frequency Processor

Control unit Datapath

– Inverse of clock ALU

period Controller Control

/Status

– Must be longer than

longest register to Registers

register delay in

entire processor PC IR

– Memory access is

often the longest I/O

Memory

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Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Pipelining: Increasing Instruction

Throughput

Wash 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

Non-pipelined Pipelined

Dry 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

non-pipelined dish cleaning pipelined dish cleaning

Time Time

Fetch-instr. 1 2 3 4 5 6 7 8

Decode 1 2 3 4 5 6 7 8

Fetch ops. Pipelined

1 2 3 4 5 6 7 8

Execute 1 2 3 4 5 6 7 8

Instruction 1

Store res. 1 2 3 4 5 6 7 8

Time

pipelined instruction execution

Embedded Systems Design: A Unified 16

Hardware/Software Introduction, (c) 2000 Vahid/Givargis 8

Superscalar and VLIW Architectures

• Performance can be improved by:

– Faster clock (but there’s a limit)

– Pipelining: slice up instruction into stages, overlap stages

– Multiple ALUs to support more than one instruction stream

• Superscalar

– Scalar: non-vector operations

– Fetches instructions in batches, executes as many as possible

• May require extensive hardware to detect independent instructions

– VLIW: each word in memory has multiple independent instructions

• Relies on the compiler to detect and schedule instructions

• Currently growing in popularity

Embedded Systems Design: A Unified 17

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Two Memory Architectures

Processor Processor

• Princeton

– Fewer memory

wires

• Harvard Program Data memory Memory

– Simultaneous memory (program and data)

program and data

memory access Harvard Princeton

Embedded Systems Design: A Unified 18

Hardware/Software Introduction, (c) 2000 Vahid/Givargis 9

Cache Memory

• Memory access may be slow Fast/expensive technology, usually on

the same chip

• Cache is small but fast Processor

memory close to processor

– Holds copy of part of memory

– Hits and misses Cache

Memory

Slower/cheaper technology, usually on

a different chip

Embedded Systems Design: A Unified 19

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Programmer’s View

• Programmer doesn’t need detailed understanding of architecture

– Instead, needs to know what instructions can be executed

• Two levels of instructions:

– Assembly level

– Structured languages (C, C++, Java, etc.)

• Most development today done using structured languages

– But, some assembly level programming may still be necessary

– Drivers: portion of program that communicates with and/or controls

(drives) another device

• Often have detailed timing considerations, extensive bit manipulation

• Assembly level may be best for these

Embedded Systems Design: A Unified 20

Hardware/Software Introduction, (c) 2000 Vahid/Givargis 10

Assembly-Level Instructions

Instruction 1 opcode operand1 operand2

Instruction 2 opcode operand1 operand2

Instruction 3 opcode operand1 operand2

Instruction 4 opcode operand1 operand2

...

• Instruction Set

– Defines the legal set of instructions for that processor

• Data transfer: memory/register, register/register, I/O, etc.

• Arithmetic/logical: move register through ALU and back

• Branches: determine next PC value when not just PC+1

Embedded Systems Design: A Unified 21

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

A Simple (Trivial) Instruction Set

Assembly instruct. First byte Second byte Operation

MOV Rn, direct Rn = M(direct)

0000 Rn direct

MOV direct, Rn M(direct) = Rn

0001 Rn direct

MOV @Rn, Rm Rm

0010 Rn M(Rn) = Rm

MOV Rn, #immed. Rn = immediate

0011 Rn immediate

ADD Rn, Rm Rn = Rn + Rm

0100 Rn Rm

SUB Rn, Rm Rn = Rn - Rm

0101 Rn Rm

JZ Rn, relative PC = PC+ relative

0110 Rn relative (only if Rn is 0)

opcode operands

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Hardware/Software Introduction, (c) 2000 Vahid/Givargis 11

Addressing Modes

Addressing Register-file Memory

Operand field

mode contents contents

Immediate Data

Register-direct Data

Register address

Register Memory address Data

Register address

indirect Data

Direct Memory address

Indirect Memory address

Memory address Data

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Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Programmer Considerations

• Program and data memory space

– Embedded processors often very limited

• e.g., 64 Kbytes program, 256 bytes of RAM (expandable)

• Registers: How many are there?

– Only a direct concern for assembly-level programmers

• I/O

– How communicate with external signals?

• Interrupts

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Hardware/Software Introduction, (c) 2000 Vahid/Givargis 12

Development Environment

• Development processor

– The processor on which we write and debug our programs

• Usually a PC

• Target processor

– The processor that the program will run on in our embedded

system

• Often different from the development processor

Development processor Target processor

Embedded Systems Design: A Unified 25

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Software Development Process

• Compilers

– Cross compiler

Asm.

C File

C File File • Runs on one

processor, but

Compiler Assembler generates code for

another

Binary

Binary

Binary File

File

File • Assemblers

Linker Debugger

Library • Linkers

Exec. Profiler

File • Debuggers

Verification Phase

Implementation Phase • Profilers

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Hardware/Software Introduction, (c) 2000 Vahid/Givargis 13


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DESCRIZIONE DISPENSA

General-Purpose Processor are:
– Processor designed for a variety of computation tasks;
– Low unit cost, in part because manufacturer spreads NRE over large numbers of units (Motorola sold half a billion 68HC05 microcontrollers in 1996 alone);
– Carefully designed since higher NRE is acceptable (can yield good performance, size and power);
– Low NRE cost, short time-to-market/prototype, high flexibility (user just writes software; no processor design);
a.k.a. microprocessor: micro used when they were implemented on one or a few chips rather than entire rooms.


DETTAGLI
Corso di laurea: Corso di laurea magistrale in ingegneria delle telecomunicazioni
SSD:
Università: L'Aquila - Univaq
A.A.: 2011-2012

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher Atreyu di informazioni apprese con la frequenza delle lezioni di Sistemi embedded e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università L'Aquila - Univaq o del prof Pomante Luigi.

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