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A simple digital camera captures images, stores images in digital format (no film; multiple images stored in camera, whose number depends on amount of memory and bits used per image), downloads images to PC. Systems-on-a-chip and high-capacity flash memory are only recently possible. There are many more features with real digital camera: variable size... Vedi di più

Esame di Sistemi embedded docente Prof. L. Pomante

Anteprima

ESTRATTO DOCUMENTO

Uploading to PC

• When connected to PC and upload command received

– Read images from memory

– Transmit serially using UART

– While transmitting

• Reset pointers, image-size variables and global memory pointer

accordingly

Embedded Systems Design: A Unified 14

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Requirements Specification

• System’s requirements – what system should do

– Nonfunctional requirements

• Constraints on design metrics (e.g., “should use 0.001 watt or less”)

– Functional requirements

• System’s behavior (e.g., “output X should be input Y times 2”)

– Initial specification may be very general and come from marketing dept.

• E.g., short document detailing market need for a low-end digital camera that:

– captures and stores at least 50 low-res images and uploads to PC,

– costs around $100 with single medium-size IC costing less that $25,

– has long as possible battery life,

– has expected sales volume of 200,000 if market entry < 6 months,

– 100,000 if between 6 and 12 months,

– insignificant sales beyond 12 months

Embedded Systems Design: A Unified 15

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Nonfunctional requirements

• Design metrics of importance based on initial specification

– Performance: time required to process image

– Size: number of elementary logic gates (2-input NAND gate) in IC

– Power: measure of avg. electrical energy consumed while processing

– Energy: battery lifetime (power x time)

• Constrained metrics

– Values must be below (sometimes above) certain threshold

• Optimization metrics

– Improved as much as possible to improve product

• Metric can be both constrained and optimization

Embedded Systems Design: A Unified 16

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Nonfunctional requirements (cont.)

• Performance

– Must process image fast enough to be useful

– 1 sec reasonable constraint

• Slower would be annoying

• Faster not necessary for low-end of market

– Therefore, constrained metric

• Size

– Must use IC that fits in reasonably sized camera

– Constrained and optimization metric

• Constraint may be 200,000 gates, but smaller would be cheaper

• Power

– Must operate below certain temperature (cooling fan not possible)

– Therefore, constrained metric

• Energy

– Reducing power or time reduces energy

– Optimized metric: want battery to last as long as possible

Embedded Systems Design: A Unified 17

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Informal functional specification

• Flowchart breaks functionality

down into simpler functions Zero-bias adjust

CCD

input

• Each function’s details could then

be described in English DCT

– Done earlier in chapter Quantize yes

no Done?

Archive in

• Low quality image has resolution memory

of 64 x 64 More Transmit serially

yes no serial output

8×8 e.g., 011010...

blocks?

• Mapping functions to a particular

processor type not done at this

stage

Embedded Systems Design: A Unified 18

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Refined functional specification

• Refine informal specification into

one that can actually be executed Executable model of digital camera

• Can use C/C++ code to describe

each function CCD.C

101011010

– Called system-level model, 110101010

010101101

prototype, or simply model ... CODEC.C

CCDPP.C

– Also is first implementation image file

• Can provide insight into operations

of system CNTRL.C 101010101

– Profiling can find computationally 010101010

101010101

intensive functions 0...

UART.C

• Can obtain sample output used to output file

verify correctness of final

implementation

Embedded Systems Design: A Unified 19

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

CCD module

• Simulates real CCD

• CcdInitialize is passed name of image file void CcdInitialize(const char *imageFileName) {

• imageFileHandle = fopen(imageFileName, "r");

CcdCapture reads “image” from file rowIndex = -1;

• CcdPopPixel outputs pixels one at a time colIndex = -1;

#include <stdio.h> }

#define SZ_ROW 64 void CcdCapture(void) {

#define SZ_COL (64 + 2) int pixel;

static FILE *imageFileHandle; rewind(imageFileHandle);

static char buffer[SZ_ROW][SZ_COL]; for(rowIndex=0; rowIndex<SZ_ROW; rowIndex++) {

static unsigned rowIndex, colIndex; for(colIndex=0; colIndex<SZ_COL; colIndex++) {

char CcdPopPixel(void) { if( fscanf(imageFileHandle, "%i", &pixel) == 1 ) {

char pixel;

pixel = buffer[rowIndex][colIndex]; buffer[rowIndex][colIndex] = (char)pixel;

if( ++colIndex == SZ_COL ) { }

colIndex = 0;

if( ++rowIndex == SZ_ROW ) { }

colIndex = -1; }

rowIndex = -1;

} rowIndex = 0;

} colIndex = 0;

return pixel;

} }

Embedded Systems Design: A Unified 20

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

CCDPP (CCD PreProcessing) module

define SZ_ROW 64

#

• Performs zero-bias adjustment #define SZ_COL 64

• CcdppCapture uses CcdCapture and CcdPopPixel to obtain static char buffer[SZ_ROW][SZ_COL];

image static unsigned rowIndex, colIndex;

• Performs zero-bias adjustment after each row read in void CcdppInitialize() {

rowIndex = -1;

void CcdppCapture(void) { colIndex = -1;

char bias; }

CcdCapture(); char CcdppPopPixel(void) {

for(rowIndex=0; rowIndex<SZ_ROW; rowIndex++) { char pixel;

for(colIndex=0; colIndex<SZ_COL; colIndex++) { pixel = buffer[rowIndex][colIndex];

buffer[rowIndex][colIndex] = CcdPopPixel(); if( ++colIndex == SZ_COL ) {

} colIndex = 0;

bias = (CcdPopPixel() + CcdPopPixel()) / 2; if( ++rowIndex == SZ_ROW ) {

for(colIndex=0; colIndex<SZ_COL; colIndex++) { colIndex = -1;

buffer[rowIndex][colIndex] -= bias; rowIndex = -1;

} }

} }

rowIndex = 0; return pixel;

colIndex = 0; }

} Embedded Systems Design: A Unified 21

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

UART module

• Actually a half UART

– Only transmits, does not receive

• UartInitialize is passed name of file to output to

• UartSend transmits (writes to output file) bytes at a time

#include <stdio.h>

static FILE *outputFileHandle;

void UartInitialize(const char *outputFileName) {

outputFileHandle = fopen(outputFileName, "w");

}

void UartSend(char d) {

fprintf(outputFileHandle, "%i\n", (int)d);

}

Embedded Systems Design: A Unified 22

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

CODEC module

static short ibuffer[8][8], obuffer[8][8], idx;

• Models FDCT encoding void CodecInitialize(void) { idx = 0; }

• ibuffer holds original 8 x 8 block void CodecPushPixel(short p) {

• obuffer holds encoded 8 x 8 block if( idx == 64 ) idx = 0;

ibuffer[idx / 8][idx % 8] = p; idx++;

• CodecPushPixel called 64 times to fill }

ibuffer with original block void CodecDoFdct(void) {

int x, y;

• CodecDoFdct called once to for(x=0; x<8; x++) {

transform 8 x 8 block for(y=0; y<8; y++)

obuffer[x][y] = FDCT(x, y, ibuffer);

– Explained in next slide }

idx = 0;

• CodecPopPixel called 64 times to }

retrieve encoded block from obuffer short CodecPopPixel(void) {

short p;

if( idx == 64 ) idx = 0;

p = obuffer[idx / 8][idx % 8]; idx++;

return p;

}

Embedded Systems Design: A Unified 23

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

CODEC (cont.)

• Implementing FDCT formula

C(h) = if (h == 0) then 1/sqrt(2) else 1.0 static const short COS_TABLE[8][8] = {

F(u,v) = ¼ x C(u) x C(v) Σ Σ D x

x=0..7 y=0..7 xy { 32768, 32138, 30273, 27245, 23170, 18204, 12539, 6392 },

cos(π(2u + 1)u/16) x cos(π(2y + 1)v/16) { 32768, 27245, 12539, -6392, -23170, -32138, -30273, -18204 },

• Only 64 possible inputs to COS, so table can { 32768, 18204, -12539, -32138, -23170, 6392, 30273, 27245 },

be used to save performance time { 32768, 6392, -30273, -18204, 23170, 27245, -12539, -32138 },

– Floating-point values multiplied by 32,678 and { 32768, -6392, -30273, 18204, 23170, -27245, -12539, 32138 },

rounded to nearest integer { 32768, -18204, -12539, 32138, -23170, -6392, 30273, -27245 },

– 32,678 chosen in order to store each value in 2 { 32768, -27245, 12539, 6392, -23170, 32138, -30273, 18204 },

bytes of memory { 32768, -32138, 30273, -27245, 23170, -18204, 12539, -6392 }

– Fixed-point representation explained more later };

• FDCT unrolls inner loop of summation, static int FDCT(int u, int v, short img[8][8]) {

implements outer summation as two double s[8], r = 0; int x;

consecutive for loops for(x=0; x<8; x++) {

s[x] = img[x][0] * COS(0, v) + img[x][1] * COS(1, v) +

static short ONE_OVER_SQRT_TWO = 23170; img[x][2] * COS(2, v) + img[x][3] * COS(3, v) +

static double COS(int xy, int uv) { img[x][4] * COS(4, v) + img[x][5] * COS(5, v) +

return COS_TABLE[xy][uv] / 32768.0; img[x][6] * COS(6, v) + img[x][7] * COS(7, v);

} }

static double C(int h) { for(x=0; x<8; x++) r += s[x] * COS(x, u);

return h ? 1.0 : ONE_OVER_SQRT_TWO / 32768.0; return (short)(r * .25 * C(u) * C(v));

} }

Embedded Systems Design: A Unified 24

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

CNTRL (controller) module

• Heart of the system void CntrlSendImage(void) {

• CntrlInitialize for consistency with other modules only for(i=0; i<SZ_ROW; i++)

for(j=0; j<SZ_COL; j++) {

• CntrlCaptureImage uses CCDPP module to input temp = buffer[i][j];

image and place in buffer UartSend(((char*)&temp)[0]); /* send upper byte */

UartSend(((char*)&temp)[1]); /* send lower byte */

• CntrlCompressImage breaks the 64 x 64 buffer into 8 x }

}

8 blocks and performs FDCT on each block using the }

CODEC module

– void CntrlCompressImage(void) {

Also performs quantization on each block for(i=0; i<NUM_ROW_BLOCKS; i++)

• CntrlSendImage transmits encoded image serially using

UART module for(j=0; j<NUM_COL_BLOCKS; j++) {

for(k=0; k<8; k++)

void CntrlCaptureImage(void) { for(l=0; l<8; l++)

CcdppCapture(); CodecPushPixel(

for(i=0; i<SZ_ROW; i++) (char)buffer[i * 8 + k][j * 8 + l]);

for(j=0; j<SZ_COL; j++) CodecDoFdct();/* part 1 - FDCT */

buffer[i][j] = CcdppPopPixel(); for(k=0; k<8; k++)

} for(l=0; l<8; l++) {

#define SZ_ROW 64 buffer[i * 8 + k][j * 8 + l] = CodecPopPixel();

#define SZ_COL 64 /* part 2 - quantization */

#define NUM_ROW_BLOCKS (SZ_ROW / 8) buffer[i*8+k][j*8+l] >>= 6;

#define NUM_COL_BLOCKS (SZ_COL / 8) }

static short buffer[SZ_ROW][SZ_COL], i, j, k, l, temp; }

void CntrlInitialize(void) {} }

Embedded Systems Design: A Unified 25

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Putting it all together

• Main initializes all modules, then uses CNTRL module to capture,

compress, and transmit one image

• This system-level model can be used for extensive experimentation

– Bugs much easier to correct here rather than in later models

int main(int argc, char *argv[]) {

char *uartOutputFileName = argc > 1 ? argv[1] : "uart_out.txt";

char *imageFileName = argc > 2 ? argv[2] : "image.txt";

/* initialize the modules */

UartInitialize(uartOutputFileName);

CcdInitialize(imageFileName);

CcdppInitialize();

CodecInitialize();

CntrlInitialize();

/* simulate functionality */

CntrlCaptureImage();

CntrlCompressImage();

CntrlSendImage();

}

Embedded Systems Design: A Unified 26

Hardware/Software Introduction, (c) 2000 Vahid/Givargis Design

• Determine system’s architecture

– Processors

• Any combination of single-purpose (custom or standard) or general-purpose processors

– Memories, buses

• Map functionality to that architecture

– Multiple functions on one processor

– One function on one or more processors

• Implementation

– A particular architecture and mapping

– Solution space is set of all implementations

• Starting point

– Low-end general-purpose processor connected to flash memory

• All functionality mapped to software running on processor

• Usually satisfies power, size, and time-to-market constraints

• If timing constraint not satisfied then later implementations could:

– use single-purpose processors for time-critical functions

– rewrite functional specification

Embedded Systems Design: A Unified 27

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Implementation 1: Microcontroller alone

• Low-end processor could be Intel 8051 microcontroller

• Total IC cost including NRE about $5

• Well below 200 mW power

• Time-to-market about 3 months

• However, one image per second not possible

– 12 MHz, 12 cycles per instruction

• Executes one million instructions per second

– CcdppCapture has nested loops resulting in 4096 (64 x 64) iterations

• ~100 assembly instructions each iteration

• 409,000 (4096 x 100) instructions per image

• Half of budget for reading image alone

– Would be over budget after adding compute-intensive DCT and

Huffman encoding

Embedded Systems Design: A Unified 28

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Implementation 2:

Microcontroller and CCDPP

EEPROM RAM

8051

UART

SOC CCDPP

• CCDPP function implemented on custom single-purpose processor

– Improves performance – less microcontroller cycles

– Increases NRE cost and time-to-market

– Easy to implement

• Simple datapath

• Few states in controller

• Simple UART easy to implement as single-purpose processor also

• EEPROM for program memory and RAM for data memory added as well

Embedded Systems Design: A Unified 29

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Microcontroller

• Synthesizable version of Intel 8051 available

– Written in VHDL

– Captured at register transfer level (RTL) Block diagram of Intel 8051 processor core

• Fetches instruction from ROM

• Decodes using Instruction Decoder 4K ROM

Instruction

Decoder

• ALU executes arithmetic operations Controller

– Source and destination registers reside in 128

ALU RAM

RAM

• Special data movement instructions used to To External Memory Bus

load and store externally

• Special program generates VHDL description

of ROM from output of C compiler/linker

Embedded Systems Design: A Unified 30

Hardware/Software Introduction, (c) 2000 Vahid/Givargis UART

• UART in idle mode until invoked

– UART invoked when 8051 executes store instruction

with UART’s enable register as target address FSMD description of UART

• Memory-mapped communication between 8051 and

all single-purpose processors invoked Start

:

• Idle

Lower 8-bits of memory address for RAM Transmi

: t LOW

I < 8

I = 0

• Upper 8-bits of memory address for memory-mapped

I/O devices Data :

Stop : Transmit

• Start state transmits 0 indicating start of byte Transmi data(I),

t HIGH then I++

I = 8

transmission then transitions to Data state

• Data state sends 8 bits serially then transitions to

Stop state

• Stop state transmits 1 indicating transmission done

then transitions back to idle mode

Embedded Systems Design: A Unified 31

Hardware/Software Introduction, (c) 2000 Vahid/Givargis CCDPP

• Hardware implementation of zero-bias operations

• Interacts with external CCD chip

– CCD chip resides external to our SOC mainly because combining

CCD with ordinary logic not feasible FSMD description of CCDPP

• Internal buffer, B, memory-mapped to 8051 C < 66

GetRow :

invoked

• Idle

Variables R, C are buffer’s row, column indices : B[R][C]=Pxl

R=0 C=C+1

C=0

• GetRow state reads in one row from CCD to B C = 66

R = 64

– 66 bytes: 64 pixels + 2 blacked-out pixels R < 64 ComputeBias :

• ComputeBias state computes bias for that row and Bias=(B[R][11] +

NextRow C < 64

: B[R][10]) / 2

stores in variable Bias R++ C=0

C=0

• FixBias

FixBias state iterates over same row subtracting :

B[R][C]=B[R][C]-Bias

C = 64

Bias from each element

• NextRow transitions to GetRow for repeat of

process on next row or to Idle state when all 64

rows completed

Embedded Systems Design: A Unified 32

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Connecting SOC components

• Memory-mapped

– All single-purpose processors and RAM are connected to 8051’s memory bus

• Read

– Processor places address on 16-bit address bus

– Asserts read control signal for 1 cycle

– Reads data from 8-bit data bus 1 cycle later

– Device (RAM or SPP) detects asserted read control signal

– Checks address

– Places and holds requested data on data bus for 1 cycle

• Write

– Processor places address and data on address and data bus

– Asserts write control signal for 1 clock cycle

– Device (RAM or SPP) detects asserted write control signal

– Checks address bus

– Reads and stores data from data bus

Embedded Systems Design: A Unified 33

Hardware/Software Introduction, (c) 2000 Vahid/Givargis Software

• System-level model provides majority of code

– Module hierarchy, procedure names, and main program unchanged

• Code for UART and CCDPP modules must be redesigned

– Simply replace with memory assignments

• xdata used to load/store variables over external memory bus

• _at_ specifies memory address to store these variables

• Byte sent to U_TX_REG by processor will invoke UART

• U_STAT_REG used by UART to indicate its ready for next byte

– UART may be much slower than processor

– Similar modification for CCDPP code

• All other modules untouched

Original code from system-level model Rewritten UART module

static unsigned char xdata U_TX_REG _at_ 65535;

#include <stdio.h> static unsigned char xdata U_STAT_REG _at_ 65534;

static FILE *outputFileHandle; void UARTInitialize(void) {}

void UartInitialize(const char *outputFileName) { void UARTSend(unsigned char d) {

outputFileHandle = fopen(outputFileName, "w"); while( U_STAT_REG == 1 ) {

} /* busy wait */

void UartSend(char d) { }

fprintf(outputFileHandle, "%i\n", (int)d); U_TX_REG = d;

} }

Embedded Systems Design: A Unified 34

Hardware/Software Introduction, (c) 2000 Vahid/Givargis


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DESCRIZIONE DISPENSA

A simple digital camera captures images, stores images in digital format (no film; multiple images stored in camera, whose number depends on amount of memory and bits used per image), downloads images to PC. Systems-on-a-chip and high-capacity flash memory are only recently possible. There are many more features with real digital camera: variable size images, image deletion, digital stretching, zooming in and out.


DETTAGLI
Corso di laurea: Corso di laurea magistrale in ingegneria delle telecomunicazioni
SSD:
Università: L'Aquila - Univaq
A.A.: 2011-2012

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher Atreyu di informazioni apprese con la frequenza delle lezioni di Sistemi embedded e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università L'Aquila - Univaq o del prof Pomante Luigi.

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