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Define system functionality convert functionality to physical implementation while satisfying constrained metrics and optimizing other design metrics. Designing embedded systems is hard because of complex functionality and Productivity gap. Hardware/software parallel evolution:
- Software design evolution (Machine instructions; Assemblers; Compilers);
- Hardware design evolution (Interconnected... Vedi di più

Esame di Sistemi embedded docente Prof. L. Pomante

Anteprima

ESTRATTO DOCUMENTO

Outline

• Automation: synthesis

• Verification: hardware/software co-simulation

Embedded Systems Design: A Unified 2

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Introduction

• Design task

– Define system functionality

– Convert functionality to physical implementation while

• Satisfying constrained metrics

• Optimizing other design metrics

• Designing embedded systems is hard

– Complex functionality

• Millions of possible environment scenarios

• Competing, tightly constrained metrics

– Productivity gap

• As low as 10 lines of code or 100 transistors produced per day

Embedded Systems Design: A Unified 3

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Improving productivity

• Design technologies developed to improve productivity

• We focus on technologies advancing hardware/software unified

view

– Automation Specification

Automation

• Program replaces manual design

• Synthesis

– Reuse Verification Reuse

Implementation

• Predesigned components

• Cores

• General-purpose and single-purpose processors on single IC

– Verification

• Ensuring correctness/completeness of each design step

• Hardware/software co-simulation

Embedded Systems Design: A Unified 4

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Automation: synthesis

• Early design mostly hardware

• Software complexity increased with advent

of general-purpose processor The codesign ladder

• Different techniques for software design

and hardware design Sequential program code (e.g., C, VHDL)

– Caused division of the two fields Behavioral synthesis

• Design tools evolve for higher levels of (1990s)

Compilers

(1960s,1970s)

abstraction Register transfers

– Different rate in each field RT synthesis

Assembly instructions (1980s, 1990s)

• Hardware/software design fields rejoining Logic equations / FSM's

– Both can start from behavioral description in Assemblers, linkers

sequential program model Logic synthesis

(1950s, 1960s) (1970s, 1980s)

– 30 years longer for hardware design to reach Machine instructions Logic gates

this step in the ladder

• Many more design dimensions Microprocessor plus VLSI, ASIC, or PLD

Implementation

program bits implementation

• Optimization critical

Embedded Systems Design: A Unified 5

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Hardware/software parallel evolution

• Software design evolution

– Machine instructions

– Assemblers The codesign ladder

• convert assembly programs into machine

instructions

– Compilers Sequential program code (e.g., C, VHDL)

• translate sequential programs into assembly Behavioral synthesis

(1990s)

• Hardware design evolution Compilers

(1960s,1970s)

– Interconnected logic gates Register transfers

– RT synthesis

Logic synthesis Assembly instructions (1980s, 1990s)

• converts logic equations or FSMs into gates Logic equations / FSM's

– Register-transfer (RT) synthesis Assemblers, linkers Logic synthesis

• converts FSMDs into FSMs, logic equations, (1950s, 1960s) (1970s, 1980s)

predesigned RT components (registers,

adders, etc.) Machine instructions Logic gates

– Behavioral synthesis Microprocessor plus VLSI, ASIC, or PLD

Implementation

program bits implementation

• converts sequential programs into FSMDs

Embedded Systems Design: A Unified 6

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Increasing abstraction level

• Higher abstraction level focus of hardware/software design evolution

– Description smaller/easier to capture

• E.g., Line of sequential program code can translate to 1000 gates

– Many more possible implementations available

• (a) Like flashlight, the higher above the ground, the more ground illuminated

– Sequential program designs may differ in performance/transistor count by orders of magnitude

– Logic-level designs may differ by only power of 2

• (b) Design process proceeds to lower abstraction level, narrowing in on single

implementation idea idea

back-of-the-envelope

decrease opportunities sequential program

increases cost modeling register-transfers

logic

implementation implementation

(b)

(a)

Embedded Systems Design: A Unified 7

Hardware/Software Introduction, (c) 2000 Vahid/Givargis Synthesis

• Automatically converting system’s behavioral description to a structural

implementation

– Complex whole formed by parts

– Structural implementation must optimize design metrics

• More expensive, complex than compilers

– Cost = $100s to $10,000s

– User controls 100s of synthesis options

– Optimization critical

• Otherwise could use software

– Optimizations different for each user

– Run time = hours, days

Embedded Systems Design: A Unified 8

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Gajski’s Y-chart

• Each axis represents type of description

– Behavioral

• Defines outputs as function of inputs

• Algorithms but no implementation Behavior

Structural

– Structural Processors, memories Sequential programs

• Implements behavior by connecting Registers, FUs, MUXs Register transfers

components with known behavior

– Physical Gates, flip-flops Logic equations/FSM

• Gives size/locations of components and Transistors Transfer functions

wires on chip/board

• Synthesis converts behavior at given level Cell Layout

to structure at same level or lower Modules

– E.g., Chips

• FSM → gates, flip-flops (same level) Boards

• FSM → transistors (lower level)

• FSM X registers, FUs (higher level) Physical

• FSM X processors, memories (higher

level)

Embedded Systems Design: A Unified 9

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Logic synthesis

• Logic-level behavior to structural implementation

– Logic equations and/or FSM to connected gates

• Combinational logic synthesis

– Two-level minimization (Sum of products/product of sums)

• Best possible performance

– Longest path = 2 gates (AND gate + OR gate/OR gate + AND gate)

• Minimize size

– Minimum cover

– Minimum cover that is prime

– Heuristics

– Multilevel minimization

• Trade performance for size

• Pareto-optimal solution

– Heuristics

• FSM synthesis

– State minimization

– State encoding

Embedded Systems Design: A Unified 10

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Technology mapping

• Library of gates available for implementation

– Simple

• only 2-input AND,OR gates

– Complex

• various-input AND,OR,NAND,NOR,etc. gates

• Efficiently implemented meta-gates (i.e., AND-OR-INVERT,MUX)

• Final structure consists of specified library’s components only

• If technology mapping integrated with logic synthesis

– More efficient circuit

– More complex problem

– Heuristics required

Embedded Systems Design: A Unified 11

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Register-transfer synthesis

• Converts FSMD to custom single-purpose processor

– Datapath

• Register units to store variables

– Complex data types

• Functional units

– Arithmetic operations

• Connection units

– Buses, MUXs

– FSM controller

• Controls datapath

– Key sub problems:

• Allocation

– Instantiate storage, functional, connection units

• Binding

– Mapping FSMD operations to specific units

Embedded Systems Design: A Unified 12

Hardware/Software Introduction, (c) 2000 Vahid/Givargis


PAGINE

25

PESO

91.23 KB

AUTORE

Atreyu

PUBBLICATO

+1 anno fa


DESCRIZIONE DISPENSA

Define system functionality convert functionality to physical implementation while satisfying constrained metrics and optimizing other design metrics. Designing embedded systems is hard because of complex functionality and Productivity gap. Hardware/software parallel evolution:
- Software design evolution (Machine instructions; Assemblers; Compilers);
- Hardware design evolution (Interconnected logic gates; Logic synthesis; Register-transfer (RT) synthesis; Behavioral synthesis).
In Gajski’s Y-chart each axis represents type of description behavioral, structural, physical, synthesis converts behavior at given level to structure at same level or lower.


DETTAGLI
Corso di laurea: Corso di laurea magistrale in ingegneria delle telecomunicazioni
SSD:
Università: L'Aquila - Univaq
A.A.: 2011-2012

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher Atreyu di informazioni apprese con la frequenza delle lezioni di Sistemi embedded e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università L'Aquila - Univaq o del prof Pomante Luigi.

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