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Define system functionality convert functionality to physical implementation while satisfying constrained metrics and optimizing other design metrics. Designing embedded systems is hard because of complex functionality and Productivity gap. Hardware/software parallel evolution:
- Software design evolution (Machine instructions; Assemblers; Compilers);
- Hardware design evolution (Interconnected... Vedi di più

Esame di Sistemi embedded docente Prof. L. Pomante

Anteprima

ESTRATTO DOCUMENTO

Hardware/software parallel evolution

• Software design evolution

– Machine instructions

– Assemblers The codesign ladder

• convert assembly programs into machine

instructions

– Compilers Sequential program code (e.g., C, VHDL)

• translate sequential programs into assembly Behavioral synthesis

(1990s)

• Hardware design evolution Compilers

(1960s,1970s)

– Interconnected logic gates Register transfers

– RT synthesis

Logic synthesis Assembly instructions (1980s, 1990s)

• converts logic equations or FSMs into gates Logic equations / FSM's

– Register-transfer (RT) synthesis Assemblers, linkers Logic synthesis

• converts FSMDs into FSMs, logic equations, (1950s, 1960s) (1970s, 1980s)

predesigned RT components (registers,

adders, etc.) Machine instructions Logic gates

– Behavioral synthesis Microprocessor plus VLSI, ASIC, or PLD

Implementation

program bits implementation

• converts sequential programs into FSMDs

Embedded Systems Design: A Unified 6

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Increasing abstraction level

• Higher abstraction level focus of hardware/software design evolution

– Description smaller/easier to capture

• E.g., Line of sequential program code can translate to 1000 gates

– Many more possible implementations available

• (a) Like flashlight, the higher above the ground, the more ground illuminated

– Sequential program designs may differ in performance/transistor count by orders of magnitude

– Logic-level designs may differ by only power of 2

• (b) Design process proceeds to lower abstraction level, narrowing in on single

implementation idea idea

back-of-the-envelope

decrease opportunities sequential program

increases cost modeling register-transfers

logic

implementation implementation

(b)

(a)

Embedded Systems Design: A Unified 7

Hardware/Software Introduction, (c) 2000 Vahid/Givargis Synthesis

• Automatically converting system’s behavioral description to a structural

implementation

– Complex whole formed by parts

– Structural implementation must optimize design metrics

• More expensive, complex than compilers

– Cost = $100s to $10,000s

– User controls 100s of synthesis options

– Optimization critical

• Otherwise could use software

– Optimizations different for each user

– Run time = hours, days

Embedded Systems Design: A Unified 8

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Gajski’s Y-chart

• Each axis represents type of description

– Behavioral

• Defines outputs as function of inputs

• Algorithms but no implementation Behavior

Structural

– Structural Processors, memories Sequential programs

• Implements behavior by connecting Registers, FUs, MUXs Register transfers

components with known behavior

– Physical Gates, flip-flops Logic equations/FSM

• Gives size/locations of components and Transistors Transfer functions

wires on chip/board

• Synthesis converts behavior at given level Cell Layout

to structure at same level or lower Modules

– E.g., Chips

• FSM → gates, flip-flops (same level) Boards

• FSM → transistors (lower level)

• FSM X registers, FUs (higher level) Physical

• FSM X processors, memories (higher

level)

Embedded Systems Design: A Unified 9

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Logic synthesis

• Logic-level behavior to structural implementation

– Logic equations and/or FSM to connected gates

• Combinational logic synthesis

– Two-level minimization (Sum of products/product of sums)

• Best possible performance

– Longest path = 2 gates (AND gate + OR gate/OR gate + AND gate)

• Minimize size

– Minimum cover

– Minimum cover that is prime

– Heuristics

– Multilevel minimization

• Trade performance for size

• Pareto-optimal solution

– Heuristics

• FSM synthesis

– State minimization

– State encoding

Embedded Systems Design: A Unified 10

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Technology mapping

• Library of gates available for implementation

– Simple

• only 2-input AND,OR gates

– Complex

• various-input AND,OR,NAND,NOR,etc. gates

• Efficiently implemented meta-gates (i.e., AND-OR-INVERT,MUX)

• Final structure consists of specified library’s components only

• If technology mapping integrated with logic synthesis

– More efficient circuit

– More complex problem

– Heuristics required

Embedded Systems Design: A Unified 11

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Register-transfer synthesis

• Converts FSMD to custom single-purpose processor

– Datapath

• Register units to store variables

– Complex data types

• Functional units

– Arithmetic operations

• Connection units

– Buses, MUXs

– FSM controller

• Controls datapath

– Key sub problems:

• Allocation

– Instantiate storage, functional, connection units

• Binding

– Mapping FSMD operations to specific units

Embedded Systems Design: A Unified 12

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Behavioral synthesis

• High-level synthesis

• Converts single sequential program to single-purpose processor

– Does not require the program to schedule states

• Key sub problems

– Allocation

– Binding

– Scheduling

• Assign sequential program’s operations to states

• Conversion template given in Ch. 2

• Optimizations important

– Compiler

• Constant propagation, dead-code elimination, loop unrolling

– Advanced techniques for allocation, binding, scheduling

Embedded Systems Design: A Unified 13

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

System synthesis

• Convert 1 or more processes into 1 or more processors (system)

– For complex embedded systems

• Multiple processes may provide better performance/power

• May be better described using concurrent sequential programs

• Tasks

– Transformation

• Can merge 2 exclusive processes into 1 process

• Can break 1 large process into separate processes

• Procedure inlining

• Loop unrolling

– Allocation

• Essentially design of system architecture

– Select processors to implement processes

– Also select memories and busses

Embedded Systems Design: A Unified 14

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

System synthesis

• Tasks (cont.)

– Partitioning

• Mapping 1 or more processes to 1 or more processors

• Variables among memories

• Communications among buses

– Scheduling

• Multiple processes on a single processor

• Memory accesses

• Bus communications

– Tasks performed in variety of orders

– Iteration among tasks common

Embedded Systems Design: A Unified 15

Hardware/Software Introduction, (c) 2000 Vahid/Givargis

System synthesis

• Synthesis driven by constraints

– E.g.,

• Meet performance requirements at minimum cost

– Allocate as much behavior as possible to general-purpose processor

• Low-cost/flexible implementation

– Minimum # of SPPs used to meet performance

• System synthesis for GPP only (software)

– Common for decades

• Multiprocessing

• Parallel processing

• Real-time scheduling

• Hardware/software codesign

– Simultaneous consideration of GPPs/SPPs during synthesis

– Made possible by maturation of behavioral synthesis in 1990’s

Embedded Systems Design: A Unified 16

Hardware/Software Introduction, (c) 2000 Vahid/Givargis


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AUTORE

Atreyu

PUBBLICATO

+1 anno fa


DESCRIZIONE DISPENSA

Define system functionality convert functionality to physical implementation while satisfying constrained metrics and optimizing other design metrics. Designing embedded systems is hard because of complex functionality and Productivity gap. Hardware/software parallel evolution:
- Software design evolution (Machine instructions; Assemblers; Compilers);
- Hardware design evolution (Interconnected logic gates; Logic synthesis; Register-transfer (RT) synthesis; Behavioral synthesis).
In Gajski’s Y-chart each axis represents type of description behavioral, structural, physical, synthesis converts behavior at given level to structure at same level or lower.


DETTAGLI
Corso di laurea: Corso di laurea magistrale in ingegneria delle telecomunicazioni
SSD:
Università: L'Aquila - Univaq
A.A.: 2011-2012

I contenuti di questa pagina costituiscono rielaborazioni personali del Publisher Atreyu di informazioni apprese con la frequenza delle lezioni di Sistemi embedded e studio autonomo di eventuali libri di riferimento in preparazione dell'esame finale o della tesi. Non devono intendersi come materiale ufficiale dell'università L'Aquila - Univaq o del prof Pomante Luigi.

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